Prosecution Insights
Last updated: October 02, 2026
Application No. 18/640,451

SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Apr 19, 2024
Priority
Apr 18, 2016 — RE 10-2016-0046972 +2 more
Examiner
NADAV, ORI
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
60%
Grant Probability
Moderate
1-2
OA Rounds
1y 4m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
426 granted / 710 resolved
At TC average
Strong +21% interview lift
Without
With
+21.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
52 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.5%
+15.5% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§103 §112
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Election/Restrictions Applicant's election with traverse of the embodiment of figure 7A in the reply filed on 11/22/2019 is acknowledged. The traversal is on the ground(s) that “If the search and examination of all the claims in an application may be made without serious burden, then the examiner must examine them on the merits. MPEP 803. Here, Applicants submit that the Office would not be unduly burdened in the examination of each pending claim, with only 3 independent and 20 total claims”. This is not found persuasive because the examination of four distinct and separate inventions does create a serious burden on the examiner. Regarding applicants’ hypothesis that “the Office would not be unduly burdened in the examination of each pending claim, with only 3 independent and 20 total claims” this does not mean that the examination of four distinct and separate inventions does create serious burden on the examiner. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of “wherein one of the plurality of first word lines and one of the plurality of second word lines that are formed on a same vertical level”, as recited in claims 1, 11 and 17, is unclear as to what is meant by having one of the plurality of first word lines and one of the plurality of second word lines that are formed on a same vertical level. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (2015/0084204) Wu (5,973,350).Regarding claims 1, 10, 11, 16, 17 and 20, Yun et al. teach in figures 2, 3, 13, 14, 16, 30, 32B, 36 and related text a semiconductor memory device comprising: a substrate including a cell region CAR and a connection region PERI (see figure 16); a first word line stack including a first ground selection line GSL, a plurality of first word lines WL on the first ground selection line GSL, and a first string selection line SSL on the plurality of first word lines (see figure 13), the plurality of first word lines 23 extending to the connection region in the first direction (being part of the peripheral region, see e.g. paragraph [0130] and figure 36); a second word line stack (another stack depicted in figure 13 having the same numericals) including a second ground selection line, a plurality of second word lines on the second ground selection line, and a second string selection line (another SSL) on the plurality of second word lines WL, the plurality of second word lines extending to the connection region in the first direction; vertical channels (see e.g. figure 14) being connected to the substrate 10 and penetrating the plurality of first word lines and the plurality of second word lines WL0, WL1; bit lines BL connecting to the vertical channels (see e.g. figures 13, 14 and 16), and an isolation region 11 on the substrate and between the first word line stack and the second word line stack; and a filler formed within the isolation region 11 and between the first ground selection line and the second ground selection line (at least element 11, see figures 2, 30 and 32B), wherein one of the plurality of first word lines and one of the plurality of second word lines that are formed on a same vertical level (see figures 14, 13) are connected to each other by a bridge (connecting wire in figure 13 and VS in figure 14 and CL in figure 3). Yun et al. do not teach that the bridge (i.e. the word line) vertically overlaps the filler (i.e. the isolation region). Wu teaches in figure 1 and related text that the bridge (i.e. the word line) 106 vertically overlaps the filler (i.e. isolation region) 109. Wu and Yun et al. are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the bridge (i.e. the word line) vertically overlaps the filler (i.e. the isolation region), as taught by Wu, in Yun et al.’s device, in order to provide better protection to the word lines. Regarding claim 18, Yun et al. do not teach in figure 3 and related text that a width of the filler in a second direction perpendicular to the first direction is greater than a width of the isolation region in the second direction. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the filler in a second direction perpendicular to the first direction greater than a width of the isolation region in the second direction, in prior’s art in order to adjust and optimize the electrical characteristics of the device. Regarding claims 2, 12 and 18, Yun et al. teach in figure 2 and related text a buffer dielectric film (30 or un-numbered gate dielectric) between the substrate 10 and the first ground selection line and the second ground selection lines. Regarding claims 3, 13 and 19, Yun et al. teach in figure 2 and related text an upper surface of the filler 11 is on substantially a same plane as an upper surface of the first ground selection line GS and the second ground selection lines. Regarding claims 4 and 14, Yun et al. teach in figures 13, 16 and related text plurality of word lines such that a third word line stack formed on the substrate and comprising a third ground selection line, a plurality of third word lines on the third ground selection line, and a third string selection line on the plurality of third word lines, the plurality of third word lines extending in the first direction; and an additional filler formed at a specific position between the second ground selection line and the third ground selection line, wherein one of the plurality of second word lines and one of the plurality of third word lines that are formed on a same vertical level are connected to each other by an additional bridge, and the additional bridge vertically overlaps the additional filler. Regarding claim 5, Yun et al. teach in figure 10 and related text that the filler 11 and the additional filler (another 11) are spaced apart along a second direction perpendicular to the first direction. Regarding claim 6, Yun et al. teach in figure 10 and related text that the filler is silicon oxide. Regarding claim 7, Yun et al. do not teach in figure 3 and related text that the filler has an H-shape in a plan view. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the filler having an H-shape in a plan view, in prior’s art in order to adjust and optimize the connection between the first and second word lines. Regarding claims 8 and 15, Yun et al. teach in figure 2 and related text that the first ground selection line and the second ground selection lines have recesses that are laterally recessed on sides thereof near the filler, and the filler at least partially fills the recesses. Regarding claim 9, Yun et al. teach in figure 10 and related text that the substrate comprises a cell region and a connection region, and the filler 11 and the bridge are in the cell region. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 8/19/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Apr 19, 2024
Application Filed
Aug 21, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+21.2%)
3y 9m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

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