DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
1. The Specification is objected because of the following reasons:
In par. 0001]: insert US Patent no. 11,990,399.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-3, 5-8, 10-12, 15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto et al. (WO 2018/030192 A1).
Re claim 1, Yamamoto teaches, under BRI, Figs. 1-4, abstract, pages 2, 3, 5 & 8, a method, comprising:
-forming patterns (e.g., patterns of 31, 32) of metallic traces on ceramic sheets (20);
-printing (e.g., screen printing) metal according to the patterns on the ceramic sheets (20) to form the metallic traces (wiring patterns 31, dummy patterns 32), the metallic traces including functional metallic traces (31) and dummy metallic traces (32);
-forming vias (e.g., via conductors) through the ceramic sheets (20); and
-stacking and aligning the ceramic sheets (20) to form a ceramic substrate (1) (Fig. 4).
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Re claim 2, Yamamoto teaches, Fig. 2, wherein spacing (between 32) of dummy metallic traces (32) has a metallic density, the metallic density is within at least 50 percent (%) of a density of the functional metallic traces.
Re claim 3, Yamamoto teaches, under BRI, Fig. 2, wherein spacing of dummy metallic traces (32) matches an average density of the metallic traces (average density of 32 of patterns 31, 32) across surfaces of the ceramic sheets (20).
Re claim 5, Yamamoto teaches, Fig. 2, page 8, wherein the patterns of the metallic traces are formed by patterning a screen for screen printing the metallic traces on the ceramic sheets (e.g., by screen printing), and wherein the metal is printed as a conductive material paste (e.g., conductive paste) through the patterned screen to provide patterned metal on the ceramic sheets (20).
Re claim 6, Yamamoto teaches electrically connecting the vias (e.g., via conductors) to the functional metallic traces (31); and electrically isolating the vias (e.g., via conductors) from the dummy metallic traces (32) (as dummy conductors).
Re claim 7, Yamamoto teaches, Fig. 4, page 5, 6th par., attaching a die (e.g., chip, not shown) to the ceramic substrate (1); electrically connect the die to the functional metallic traces (31); and electrically isolating the die from the dummy metallic traces (via ceramic insulating layers).
Re claim 8, Yamamoto teaches, Fig. 4, wherein the dummy metallic traces (32) comprise first dummy metallic trances (in 10a) and a second dummy metallic traces (in 11) having a second density, the second density different than the first density.
Re claims 10 & 11, Yamamoto teaches, Fig. 4, wherein the ceramic sheets comprises a first ceramic sheet (10c) and a second ceramic sheet (10b), the functional metallic traces (31) comprise first functional metallic traces (31) on the first ceramic sheet (10c) and second functional metallic traces (31) on the second ceramic sheet (10c), the dummy metallic traces (32) comprise first dummy metallic traces (32) on the first ceramic sheet (10c) and second dummy metallic traces (32) on the second ceramic sheet (10b); wherein a first density of the first dummy metallic traces (32 in 10c) is different than a second density of the second dummy metallic traces (32 in 10b).
Re claims 12 & 15, Yamamoto teaches, under BRI, Fig. 4, abstract, pages 2, 3 & 5, a method, comprising:
-obtaining a substrate layer (20 or 12), wherein the substrate layer (20 or 12) is ceramic (e.g., ceramic insulating layer); and
-forming metallic traces (31, 32) on the substrate layer (20 or 12), wherein the metallic traces comprise functional metallic traces (31), first dummy metallic traces (32 in 10c), and second dummy metallic traces (32 in 10b), wherein the first dummy metallic traces (32 in 10c) have a first density, the second dummy metallic traces (32 in 10b) have a second density, and the second density is different than the first density.
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Re claim 17, Yamamoto teaches, Fig. 4, page 5, 6th par., attaching a die (e.g., chip, not shown) to the substrate (20, 12); and electrically coupling the die to the functional metallic traces (31) (as active conductors).
Re claim 18, Yamamoto teaches, Fig. 4, wherein the first dummy metallic traces (32 in 10c) are electrically isolated (via insulating layer) from the second dummy metallic traces (32 in 10b) and the functional metallic traces (31).
Re claim 19, Yamamoto teaches, under BRI, Figs. 1-4, abstract, pages 2, 3 & 5 a method, comprising:
-forming first metallic traces (31, 32) on a first ceramic sheet (20 of 10c), the first metallic traces (31, 32) comprising first functional traces (31) and first dummy traces (32);
-forming second metallic traces (31, 32) on a second ceramic sheet (20 of 10b), the second metallic traces (31, 32) comprising second functional traces (31) and second dummy traces (32); and
-stacking the second ceramic sheet (20 of 10b) on the first ceramic sheet (20 of 10c) to produce a ceramic substrate (1).
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Re claim 20, Yamamoto teaches wherein a first density of the first dummy traces (32 in 10c) is different than a second density of the second dummy traces (32 in 10b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Yoshimura et al. (US 2005/0018020).
The teachings of Yamamoto have been discussed above.
Re claim 4, Yamamoto does not explicitly teach wherein the patterns of the metallic traces are formed by patterning a resist layer of the metallic traces on the ceramic sheets, and wherein the metal is printed by depositing the metal over the patterned resist layer and removing the resist layer to provide a patterned metal layer on the ceramic sheets.
Yoshimura teaches screen printing process [0036] & “ A plating resist layer having openings of predetermined shape is formed on the surface of the piezoelectric ceramic layer 22 by photolithography or the like, the surface is then plated and the resist layer is removed, and the surface is formed into a predetermined shape” [0038].
As taught by Yoshimura, one of ordinary skill in the art would utilize & modify the above teaching to obtain the patterns of the metallic traces are formed by patterning a resist layer of the metallic traces on the ceramic sheets, and wherein the metal is printed by depositing the metal over the patterned resist layer and removing the resist layer to provide a patterned metal layer on the ceramic sheets as claimed, because patterned resist layer is known & widely used in art as mask to achieve desired patterns of materials on a surface of a layer/film.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Yoshimura in combination Yamamoto due to above reason.
4. Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Koubuchi et al. (US 6,261,883).
The teachings of Yamamoto have been discussed above.
Re claim 9, Yamamoto does not explicitly teach wherein the dummy metallic traces have a first density, the functional metallic traces have a second density, and the first density match the second destiny.
Koubuchi teaches, under BRI, Fig. 4, the dummy metallic traces (18 at center) have a first density, the functional metallic traces (17 at center) have a second density, and the first density match the second destiny.
As taught by Koubuchi, one of ordinary skill in the art would utilize & modify the above teaching to obtain the dummy metallic traces have a first density, the functional metallic traces have a second density, and the first density match the second destiny as claimed, because it aids in preventing the formation of a sparse portion, and improving reliability of the formed circuit device. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Koubuchi in combination Yamamoto due to above reason.
Re claim 16, in combination cited above, Koubuchi teaches, Fig. 4, wherein the first density (of 18 in center) matches a third density of the functional metallic traces (of 17 in center).
5. Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Martin (US 5,224,017).
The teachings of Yamamoto have been discussed above.
Re claims 13 & 14, Yamamoto does not explicitly teach wherein the substrate layer is a printed circuit board; is a silicon-based circuit board.
Martin teaches the use of printed circuit board (col. 5, 3rd par.) and silicon based circuit board (col. 1, last par.).
As taught by Martin, one of ordinary skill in the art would utilize & modify the above teaching to obtain a printed circuit board & a silicon-based circuit board as claimed, because they are known and widely used in the art to improve density integration & performance in the formed devices/integrated circuits.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Martin in combination Yamamoto due to above reason.
6. Claims 1, 6, 7, 12, 15 and 17-19 are, in alternative consideration, rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto in view of Amand et al. (US 7,755,176).
Re claim 1, Yamamoto teaches, under BRI, Figs. 1-4, abstract, pages 2, 3, 5 & 8, a method, comprising:
-forming patterns (e.g., patterns of 31, 32) of metallic patterns on ceramic sheets (20);
-printing (e.g., screen printing) metal according to the patterns on the ceramic sheets (20) to form the metallic patterns (31, 32), the metallic patterns including functional metallic patterns (31) and dummy metallic patterns (32);
-forming vias (e.g., via conductors) through the ceramic sheets (20); and
-stacking and aligning the ceramic sheets (20) to form a ceramic substrate (1) (Fig. 4).
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Yamamoto does not explicitly teach metallic traces.
Amand teaches, Fig. 10, metallic traces (signal traces 120, dummy traces 130) (col. 3, lines 24-25).
As taught by Amand, one of ordinary skill in the art would utilize & modify the above teaching to obtain metallic traces as claimed, because metallic traces are known conductive features in circuitry to provide electrical connections.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Amand in combination Yamamoto due to above reason.
Re claim 6, in combination cited above, Amand teaches, Fig. 10, electrically connecting the vias (123) to the functional metallic traces (120); and electrically isolating the vias (123) from the dummy metallic traces (130).
Re claim 7, in combination cited above, Amand teaches, Fig. 10, attaching a die (150) to the ceramic substrate (see Yamamoto’s teaching); electrically connecting the die (150) to the functional metallic traces (120); and electrically isolating the die (150) from the dummy metallic traces (130).
Re claims 12 & 15, Yamamoto teaches, under BRI, Fig. 4, abstract, pages 2, 3 & 5, a method, comprising:
-obtaining a substrate layer (20 or 12), wherein the substrate layer (20 or 12) is ceramic (e.g., ceramic insulating layer); and
-forming metallic traces (31, 32) on the substrate layer (20 or 12), wherein the metallic patterns comprise functional metallic patterns (31), first dummy metallic patterns (32 in 10c), and second dummy metallic patterns (32 in 10b), wherein the first dummy metallic patterns (32 in 10c) have a first density, the second dummy metallic patterns (32 in 10b) have a second density, and the second density is different than the first density.
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Yamamoto does not explicitly teach metallic traces.
Amand teaches, Fig. 10, metallic traces (signal traces 120, dummy traces 130) (col. 3, lines 24-25).
As taught by Amand, one of ordinary skill in the art would utilize & modify the above teaching to obtain metallic traces as claimed, because metallic traces are known conductive features in circuitry to provide electrical connections.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Amand in combination Yamamoto due to above reason.
Re claim 17, in combination cited above, Amand teaches, Fig. 10, attaching a die (150) to the substrate (100); and electrically coupling the die (100) to the functional metallic traces (120).
Re claim 18, in combination cited above, Amand teaches, Fig. 10, wherein the first dummy metallic traces (left group 130) are electrically isolated from the second dummy electrical traces (right group 130) and the functional metallic traces (120).
Re claim 19, Yamamoto teaches, under BRI, Figs. 1-4, abstract, pages 2, 3 & 5 a method, comprising:
-forming first metallic patterns (31, 32) on a first ceramic sheet (20 of 10c), the first metallic patterns (31, 32) comprising first functional patterns (31) and first dummy patterns (32);
-forming second metallic patterns (31, 32) on a second ceramic sheet (20 of 10b), the second metallic patterns (31, 32) comprising second functional patterns (31) and second dummy patterns (32); and
-stacking the second ceramic sheet (20 of 10b) on the first ceramic sheet (20 of 10c) to produce a ceramic substrate (1).
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Yamamoto does not explicitly teach functional & dummy traces.
Amand teaches, Fig. 10, functional and dummy traces (signal traces 120, dummy traces 130) (col. 3, lines 24-25).
As taught by Amand, one of ordinary skill in the art would utilize & modify the above teaching to obtain functional & dummy traces as claimed, because metallic/conductive traces are known conductive features in circuitry to provide electrical connections.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Amand in combination Yamamoto due to above reason.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 6/3/26
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