Prosecution Insights
Last updated: April 19, 2026
Application No. 18/640,555

PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING THE SAME

Non-Final OA §103§112
Filed
Apr 19, 2024
Examiner
VARGHESE, ROSHN K
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
87%
With Interview

Examiner Intelligence

Grants 66% — above average
66%
Career Allow Rate
491 granted / 738 resolved
-1.5% vs TC avg
Strong +21% interview lift
Without
With
+20.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
39 currently pending
Career history
777
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
27.5%
-12.5% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 738 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 13 lack a unit of measurement for the glass transition temperature. It is unclear from the Applicant’s Specification nor claims as to the unit of measurement for the glass transition temperature. It is unclear as to the claimed value of the glass transition temperature. Temperature can be typically measured in Fahrenheit (°F) or Celsius (°C) or Kelvin (K) however the current application is silent as to the unit of measurement of the glass transition temperature. Note that no new matter should be added nor entered. Claims 2 – 12 and 14 – 20 are rejected due to dependency from claims 1 and 13. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1 – 9 and 11 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0059863 A1) in view of Lee (US 2020/0042125 A1). Regarding Claim 1, Kim (US 2024/0059863 A1) discloses an electronic device (Fig 7), comprising: a printed circuit board (Fig 7; [0159]) and including an alternately stacked plurality of insulation layers (450,440,430,420,410) and plurality of conductive layers (500), wherein the plurality of insulation layers include at least one first insulation layer (420) and at least one second insulation layer (430), wherein the at least one first insulation layer (420) includes a first insulator including a resin ([0160,0170-0172]) having a glass transition temperature (Tg) value of 200 degrees or more (see Table 3; “228” °C). Kim does not disclose in Fig 7, a housing; and a printed circuit board disposed in the housing and does not explicitly disclose a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber. However Kim also teaches of an electronic device, comprising: and a printed circuit board (Fig 4; [0119]) and including an alternately stacked plurality of insulation layers (311,312,313,314,321,322,331,332) and plurality of conductive layers (340), wherein the plurality of insulation layers include at least one first insulation layer (320,330) and at least one second insulation layer (310), wherein the at least one first insulation layer includes a first insulator (320,330) including a resin ([0119]) having a glass transition temperature (Tg) value (composition would comprise some glass transition temperature) and a filler ([0101-0114]) having a content of 50% to 70% ([0105]), and wherein the at least one second insulation layer (310) includes a second insulator including a glass fiber ([0119-0128]). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Kim (Fig 7), comprising a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber as taught by Kim (Fig 4), as both limitations are present in the same publication and in order to meet a desired strength, meet a desired coefficient of thermal expansion, reach a desired dielectric constant, reduce thickness, prevent cracks, prevent damage to circuit patterns, prevent dielectric constant destruction, and improve reliability (Kim, [0078,0084,0093,0094,0119-0128]). Lee (US 2020/0042125 A1) teaches of an electronic device (Fig 1-2), comprising: a housing (1; see structure 1 shown at least partially housing circuit board 90; [0070]); and a printed circuit board (90) disposed in the housing (1). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim, comprising: a housing and a printed circuit board disposed in the housing as taught by Lee, in order to provide a user interface allowing input means and protection (Lee, [0003-0009,0080,0096]) and furthermore a housing would provide environmental protection of the circuit board (Lee, [0003-0009,0080,0096]). Note that the claim has not structurally defined the housing. Regarding Claim 2, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein the first insulator (320,330) does not include a glass fiber ([0119]). Regarding Claim 3, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein the at least one first insulation layer (320,330) has a thickness of 20 μm or less ([0121-0125]). Regarding Claim 4, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein a permittivity (Dk) of the first insulator is 3.0 or less ([0070-0071,0082]). Regarding Claim 5, Kim in view of Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions. Kim does not explicitly disclose the electronic device of claim 1, wherein a size of the printed circuit board is 400 mm2 or more. It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim in view of Lee, wherein a size of the printed circuit board is 400 mm2 or more, in order to provide sufficient space to mount a plurality of components onto the boards and thus increase the functional capability of the circuit board and device, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification pp. 21-22, [73-75]) Applicant has not disclosed any criticality for the claimed limitations. Regarding Claim 6, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 312) positioned at a center (see Fig 4; note that the structural limits of the claimed center are not defined nor a datum of reference claimed) with respect to a stacking direction of the printed circuit board comprises the second insulator (310). Regarding Claim 7, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 311 or 314) positioned at an upper or lower side with respect to a stacking direction of the printed circuit board comprises the second insulator (310). Regarding Claim 8, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein the at least one second insulation layer (310) has a thickness of 20 μm or more ([0121]). Regarding Claim 9, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein the printed circuit board further includes at least one via hole (350) penetrating the at least one first insulation layer (310) or the at least one second insulation layer (320,330). Regarding Claim 11, The electronic device of claim 1, wherein the printed circuit board has a rigidity of 430,000 (N/m) or more. Kim in view of Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions. Kim does not explicitly disclose the electronic device of claim 1, wherein the printed circuit board has a rigidity of 430,000 (N/m) or more. The Office realizes that all of the claimed effects or physical properties are not positively stated by the reference(s). However, the references render obvious all of the claimed ingredients, in the claimed amounts, process steps, and process conditions. Furthermore there is nothing in Applicant’s original specification to indicate that the claimed properties are the result of anything other than mixing of the claimed ingredients in the claimed amounts. Therefore, the claimed effects and physical properties, i.e. a rigidity of 430,000 (N/m) or more, would implicitly be achieved by a wire and rendered obvious. See MPEP 2112.01. If it is the applicant’s position that this would not be the case: (1) evidence would need to be provided to support the applicant’s position; and (2) it would the Office’s position that the application contains inadequate disclosure that there is no teaching as to how to obtain the claimed properties with only the claimed ingredients. It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim in view of Lee, wherein the printed circuit board has a rigidity of 430,000 (N/m) or more, in order to provide sufficient strength to mount a plurality of components onto the board without forming cracks or breaks in the supporting board, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, (see Applicant’s Specification p. 26, [92], p. 29, [101], p.31 [109] and p. 33 [116]) Applicant has not disclosed any criticality for the claimed limitations. Regarding Claim 12, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 1, wherein the plurality of conductive layers (340) include at least three conductive layers (see Fig 4 showing a plurality of layers of 340), and wherein the plurality of insulating layers include at least two insulating layers (311,312) alternately stacked between two of the at least three conductive layers (340). Regarding Claim 13, Kim discloses an electronic device (Fig 7), comprising: a printed circuit board (Fig 7; [0159]) and including an alternately stacked plurality of insulation layers (450,440,430,420,410) and plurality of conductive layers (500), wherein the plurality of insulation layers include at least one first insulation layer (420) having a first thickness and at least one second insulation (430) layer having a second thickness (see Fig 7), wherein the at least one first insulation layer (420) includes a first insulator including a resin ([0160,0170-0172]) having a glass transition temperature (Tg) value of 200 degrees or more (see Table 3; “228” °C). Kim does not disclose in Fig 7, a housing; and a printed circuit board disposed in the housing and does not explicitly disclose at least one first insulation layer having a first thickness and at least one second insulation layer having a second thickness greater than the first thickness, a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber. However Kim also teaches of an electronic device, comprising: a printed circuit board (Fig 4; [0119]) and including an alternately stacked plurality of insulation layers (311,312,313,314,321,322,331,332) and plurality of conductive layers (340), wherein the plurality of insulation layers include at least one first insulation layer (320,330) having a first thickness ([0123-125]) and at least one second insulation (310) layer having a second thickness ([0121]) greater than the first thickness wherein the at least one first insulation layer includes a first insulator (320,330) including a resin ([0119]) having a glass transition temperature (Tg) value (composition would comprise some glass transition temperature) and a filler ([0101-0114]) having a content of 50% to 70% ([0105]), and wherein the at least one second insulation layer (310) includes a second insulator including a glass fiber ([0119-0128]). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Kim (Fig 7), wherein the plurality of insulation layers include at least one first insulation layer having a first thickness and at least one second insulation layer having a second thickness greater than the first thickness and comprising a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber as taught by Kim (Fig 4), as both limitations are present in the same publication and in order to meet a desired strength, meet a desired coefficient of thermal expansion, reach a desired dielectric constant, reduce overall thickness, prevent cracks, prevent damage to circuit patterns, prevent dielectric constant destruction, and improve reliability (Kim, [0078,0084,0093,0094,0119-0128]). Lee (US 2020/0042125 A1) teaches of an electronic device (Fig 1-2), comprising: a housing (1; see structure 1 shown at least partially housing circuit board 90; [0070]); and a printed circuit board (90) disposed in the housing (1). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim, comprising: a housing and a printed circuit board disposed in the housing as taught by Lee, in order to provide a user interface allowing input means and protection (Lee, [0003-0009,0080,0096]) and furthermore a housing would provide environmental protection of the circuit board (Lee, [0003-0009,0080,0096]). Note that the claim has not structurally defined the housing. Regarding Claim 14, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the first insulator (320,330) does not include a glass fiber ([0119]). Regarding Claim 15, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the at least one first insulation layer (320,330) has a thickness of 20 μm or less ([0121-0125]). Regarding Claim 16, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein a permittivity (Dk) of the first insulator is 3.0 or less ([0070-0071,0082]). Regarding Claim 17, Kim in view of Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions. Kim does not explicitly disclose the electronic device of claim 13, wherein a size of the printed circuit board is 400 mm2 or more. It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim in view of Lee, wherein a size of the printed circuit board is 400 mm2 or more, in order to provide sufficient space to mount a plurality of components onto the boards and thus increase the functional capability of the circuit board and device, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification pp. 21-22, [73-75]) Applicant has not disclosed any criticality for the claimed limitations. Regarding Claim 18, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 312) positioned at a center (see Fig 4; note that the structural limits of the claimed center are not defined nor a datum of reference claimed) with respect to a stacking direction of the printed circuit board comprises the second insulator (310). Regarding Claim 19, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 311 or 314) positioned at an upper or lower side with respect to a stacking direction of the printed circuit board comprises the second insulator (310). Regarding Claim 20, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the at least one second insulation layer (310) has a thickness of 20 μm or more ([0121]). Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0059863 A1) in view of Lee (US 2020/0042125 A1) as applied to claim 1 above and further in view of Tokiwa (US 2013/0266779 A1). Regarding Claim 10, Kim in view of Lee teaches the limitations of the preceding claim. Kim does not explicitly disclose the electronic device of claim 1, wherein a dielectric loss (Df) of the first insulator is 0.005 or less. Tokiwa (US 2013/0266779 A1) teaches of a device ([0001-0003,0043,0120]) wherein a dielectric loss (Df) of the first insulator is 0.005 or less (Abstract, [0025,0049,0059]). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim in view of Lee, wherein a dielectric loss (Df) of the first insulator is 0.005 or less as taught by Tokiwa, in order to enable speeding up of signal transmission and overall improve signals in a circuit board (Tokiwa, [0025,0049,0059]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Japp (US 2008/0003407 A1) teaches of an electronic device, comprising: at least one first insulation layer includes a first insulator including a resin having a glass transition temperature (Tg) value of 200 degrees or more ([0035]) and a filler ([0033]) having a content, and dielectric loss of 0.005 (claim 1). This could be used in a 103 Rejection. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROSHN K VARGHESE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Apr 19, 2024
Application Filed
Feb 25, 2026
Non-Final Rejection — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
87%
With Interview (+20.6%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 738 resolved cases by this examiner. Grant probability derived from career allow rate.

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