DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Note that no arguments were made with respect to amendments to claim 13 including identical language of original claim 19. Applicant should submit an argument under the heading “Remarks” pointing out disagreements with the examiner’s contentions. Applicant must also discuss the references applied against the claims, explaining how the claims avoid the references or distinguish from them.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 3, 5, 8, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (US 2019/0214321 A1) in view of Yun (US 2021/0114348 A1) and Lee (US 2020/0042125 A1).
Regarding Claim 1, Ito (US 2019/0214321 A1) discloses an electronic device (Fig 1), comprising: a printed circuit board (1) and including an alternately stacked plurality of insulation layers (410,51,52) and plurality of conductive layers (3,9), wherein the plurality of insulation layers include at least one first insulation layer (410) and at least one second insulation layer (51,52,8), wherein the at least one first insulation layer (410) includes a first insulator including a resin having a glass transition temperature value ([0048]) and a filler ([0039]) having a content of 50% to 70% ([0036-0039]; e.g. 200 parts by mass of filler /300 parts by mass of filler and resin), and wherein the at least one second insulation layer (51,52) includes a second insulator including a glass fiber (8; [0043]), and wherein among the plurality of insulation layers, an insulation layer (51,52,8) positioned at an uppermost (51) or lowermost (52) side with respect to a stacking direction of the printed circuit board comprises the second insulator (51,52,8).
Ito does not disclose a housing; and a printed circuit board disposed in the housing and does not explicitly disclose a resin having a glass transition temperature value of 200 degrees Celsius or more.
Yun (US 2021/0114348 A1) teaches of an electronic device ([0025,0034] Table 3), comprising: wherein at least one first insulation layer includes a first insulator including a resin ([0032-0102]) having a glass transition temperature value of 200 degrees Celsius or more ([0122], Table 3) and a filler having a content of 50% to 70% ([0092-0095]; e.g. 200 parts by mass of filler /300 parts by mass of filler and resin).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Ito, wherein the at least one first insulation layer includes a first insulator including a resin having a glass transition temperature value of 200 degrees Celsius or more as taught by Yun, in order to improve reliability, to improve performance, improve flowability, increase pattern-filling property, provide excellent thermal properties, provide excellent mechanical properties, increase a working temperature range, improve glass transition temperature, achieve appropriate levels of flowability, provide high thermal stability, achieve mechanical properties, improve mechanical strength, widen a window to maintain minimum viscosity, reduce overall thickness, improve stability, and improve storability (Yun, [0006-0012, 0032-0033,0076,0091-0095,0101-0102,0121-0123,0135]).
Lee (US 2020/0042125 A1) teaches of an electronic device (Fig 1-2), comprising: a housing (1; see structure 1 shown at least partially housing circuit board 90; [0070]); and a printed circuit board (90) disposed in the housing (1).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun, comprising: a housing and a printed circuit board disposed in the housing as taught by Lee, in order to provide a user interface allowing input means and protection (Lee, [0003-0009,0080,0096]) and furthermore a housing would provide environmental protection of the circuit board (Lee, [0003-0009,0080,0096]). Note that the claim has not structurally defined the housing.
Regarding Claim 2, Ito in view of Yun and Lee teaches the limitations of the preceding claim and Ito further teaches the electronic device (Fig 1) of claim 1, wherein the first insulator (410) does not include a glass fiber (see Fig 1 showing no 8 in layer 4).
Regarding Claim 3, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein the at least one first insulation layer has a thickness of 20 μm or less.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein the at least one first insulation layer has a thickness of 20 μm or less in order to meet modern demands of smaller and more portable electronic devices, for example a mobile smartphone while still providing support for mounting electronics onto a circuit board, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification p. 25, [89]) Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 5, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein a size of the printed circuit board is 400 mm2 or more.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein a size of the printed circuit board is 400 mm2 or more, in order to provide sufficient space to mount a plurality of components onto the boards and thus increase the functional capability of the circuit board and device, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification pp. 21-22, [73-75]) Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 8, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein the at least one second insulation layer has a thickness of 20 μm or more.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein the at least one second insulation layer has a thickness of 20 μm or more in order to provide structural support for mounting electronics onto a circuit board without warpage or damage, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification p. 25, [89]) Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 11, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein the printed circuit board has a rigidity of 430,000 (N/m) or more.
The Office realizes that all of the claimed effects or physical properties are not positively stated by the reference(s). However, the references render obvious all of the claimed ingredients, in the claimed amounts, process steps, and process conditions. Furthermore there is nothing in Applicant’s original specification to indicate that the claimed properties are the result of anything other than mixing of the claimed ingredients in the claimed amounts. Therefore, the claimed effects and physical properties, i.e. a rigidity of 430,000 (N/m) or more, would implicitly be achieved by a wire and rendered obvious. See MPEP 2112.01. If it is the applicant’s position that this would not be the case: (1) evidence would need to be provided to support the applicant’s position; and (2) it would the Office’s position that the application contains inadequate disclosure that there is no teaching as to how to obtain the claimed properties with only the claimed ingredients.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein the printed circuit board has a rigidity of 430,000 (N/m) or more, in order to provide sufficient strength to mount a plurality of components onto the board without forming cracks or breaks in the supporting board, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, (see Applicant’s Specification p. 26, [92], p. 29, [101], p.31 [109] and p. 33 [116]) Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 12, Ito in view of Yun and Lee teaches the limitations of the preceding claim and Ito further teaches the electronic device (Fig 1) of claim 1, wherein the plurality of conductive layers (3,9,3) include at least three conductive layers (see Fig 1 showing 9,3,3), and wherein the plurality of insulating layers include at least two insulating layers (51,410) alternately stacked between two of the at least three conductive layers (3,9).
Claim(s) 4, 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (US 2019/0214321 A1) in view of Yun (US 2021/0114348 A1) and Lee (US 2020/0042125 A1) as applied to claim 1 above and further in view of Kim (US 2024/0059863 A1).
Regarding Claim 4, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein a permittivity (Dk) of the first insulator is 3.0 or less.
Kim (US 2024/0059863 A1) teaches of an electronic device (Fig 4), wherein a permittivity (Dk) of a first insulator is 3.0 or less ([0070-0071,0082]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein a permittivity (Dk) of the first insulator is 3.0 or less as taught by Kim, in order to suit high frequency applications (Kim, [0070-0082]).
Regarding Claim 6, Ito in view of Yun and Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Ito does not explicitly disclose the electronic device of claim 1, wherein among the plurality of insulation layers, an insulation layer positioned at a center with respect to a stacking direction of the printed circuit board comprises the second insulator.
Kim (US 2024/0059863 A1) teaches of an electronic device (Fig 4), wherein among a plurality of insulation layers (310,320,330), an insulation layer (e.g. 312,313) positioned at a center (see Fig 4; note that the structural limits of the claimed center are not defined nor a datum of reference claimed) with respect to a stacking direction of the printed circuit board comprises a second insulator (310; [0119]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein among the plurality of insulation layers, an insulation layer positioned at a center with respect to a stacking direction of the printed circuit board comprises the second insulator as taught by Kim, in order to meet a desired strength, meet a desired coefficient of thermal expansion, reach a desired dielectric constant, reduce overall thickness, prevent cracks, prevent damage to circuit patterns, prevent dielectric constant destruction, and improve reliability (Kim, [0078,0084,0093,0094,0119-0128]).
Regarding Claim 9, Ito in view of Yun and Lee teaches the limitations of the preceding claim.
Ito does not disclose the electronic device of claim 1, wherein the printed circuit board further includes at least one via hole penetrating the at least one first insulation layer or the at least one second insulation layer.
Kim (US 2024/0059863 A1) teaches of an electronic device (Fig 4), wherein the printed circuit board further includes at least one via hole (350) penetrating the at least one first insulation layer (310) or the at least one second insulation layer (320,330).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein the printed circuit board further includes at least one via hole penetrating the at least one first insulation layer or the at least one second insulation layer as taught by Kim, in order to electrically connect circuit patterns disposed on different surfaces to one another (Kim, [0141]). Note that this would provide additional functionality to the printed circuit board providing more applications of the electronic device.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ito (US 2019/0214321 A1) in view of Yun (US 2021/0114348 A1) and Lee (US 2020/0042125 A1) as applied to claim 1 above and further in view of Tokiwa (US 2013/0266779 A1).
Regarding Claim 10, Ito in view of Yun and Lee teaches the limitations of the preceding claim.
Ito does not explicitly disclose the electronic device of claim 1, wherein a dielectric loss (Df) of the first insulator is 0.005 or less.
Tokiwa (US 2013/0266779 A1) teaches of a device ([0001-0003,0043,0120]) wherein a dielectric loss (Df) of the first insulator is 0.005 or less (Abstract, [0025,0049,0059]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Ito in view of Yun and Lee, wherein a dielectric loss (Df) of the first insulator is 0.005 or less as taught by Tokiwa, in order to enable speeding up of signal transmission and overall improve signals in a circuit board (Tokiwa, [0025,0049,0059]).
Claim(s) 13 – 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2024/0059863 A1) in view of Lee (US 2020/0042125 A1).
Regarding Claim 13, Kim discloses an electronic device (Fig 7), comprising: a housing; and a printed circuit board disposed in the housing and including an alternately stacked plurality of insulation layers (450,440,430,420,410) and plurality of conductive layers (500), wherein the plurality of insulation layers include at least one first insulation layer (420) having a first thickness and at least one second insulation (430) layer having a second thickness (see Fig 7), wherein the at least one first insulation layer (420) includes a first insulator including a resin ([0160,0170-0172]) having a glass transition temperature (Tg) value of 200 degrees Celsius or more (see Table 3; “228” °C).
Kim does not disclose in Fig 7, a housing; and a printed circuit board disposed in the housing and does not explicitly disclose at least one first insulation layer having a first thickness and at least one second insulation layer having a second thickness greater than the first thickness, a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber, wherein among the plurality of insulation layers, an insulation layer positioned at an upper or lower side with respect to a stacking direction of the printed circuit board comprises the second insulator.
However Kim also teaches of an electronic device, comprising: a printed circuit board (Fig 4; [0119]) and including an alternately stacked plurality of insulation layers (311,312,313,314,321,322,331,332) and plurality of conductive layers (340), wherein the plurality of insulation layers include at least one first insulation layer (320,330) having a first thickness ([0123-125]) and at least one second insulation (310) layer having a second thickness ([0121]) greater than the first thickness wherein the at least one first insulation layer includes a first insulator (320,330) including a resin ([0119]) having a glass transition temperature (Tg) value (composition would comprise some glass transition temperature) and a filler ([0101-0114]) having a content of 50% to 70% ([0105]), and wherein the at least one second insulation layer (310) includes a second insulator including a glass fiber ([0119-0128]), wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 311 or 314) positioned at an upper (e.g. 311 is towards an upper side of 312 which is part of the overall PCB; 311 is up from a central point of the PCB stack and therefore towards an upper side) or lower side (e.g. 314 is towards an upper side of 312 which is part of the overall PCB; 314 is lower from a central point of the PCB stack and therefore at a lower side) with respect to a stacking direction of the printed circuit board comprises the second insulator (310).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Kim (Fig 7), wherein the plurality of insulation layers include at least one first insulation layer having a first thickness and at least one second insulation layer having a second thickness greater than the first thickness and comprising a filler having a content of 50% to 70%, and wherein the at least one second insulation layer includes a second insulator including a glass fiber, wherein among the plurality of insulation layers, an insulation layer positioned at an upper or lower side with respect to a stacking direction of the printed circuit board comprises the second insulator as taught by Kim (Fig 4), as both limitations are present in the same publication and in order to meet a desired strength, meet a desired coefficient of thermal expansion, reach a desired dielectric constant, reduce overall thickness, prevent cracks, prevent damage to circuit patterns, prevent dielectric constant destruction, and improve reliability (Kim, [0078,0084,0093,0094,0119-0128]).
Lee (US 2020/0042125 A1) teaches of an electronic device (Fig 1-2), comprising: a housing (1; see structure 1 shown at least partially housing circuit board 90; [0070]); and a printed circuit board (90) disposed in the housing (1).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim, comprising: a housing and a printed circuit board disposed in the housing as taught by Lee, in order to provide a user interface allowing input means and protection (Lee, [0003-0009,0080,0096]) and furthermore a housing would provide environmental protection of the circuit board (Lee, [0003-0009,0080,0096]). Note that the claim has not structurally defined the housing.
Regarding Claim 14, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the first insulator (320,330) does not include a glass fiber ([0119]).
Regarding Claim 15, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the at least one first insulation layer (320,330) has a thickness of 20 μm or less ([0121-0125]).
Regarding Claim 16, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein a permittivity (Dk) of the first insulator is 3.0 or less ([0070-0071,0082]).
Regarding Claim 17, Kim in view of Lee teaches the limitations of the preceding claim, including the claimed materials and claimed proportions.
Kim does not explicitly disclose the electronic device of claim 13, wherein a size of the printed circuit board is 400 mm2 or more.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Kim in view of Lee, wherein a size of the printed circuit board is 400 mm2 or more, in order to provide sufficient space to mount a plurality of components onto the boards and thus increase the functional capability of the circuit board and device, since such a modification would have involved a mere change in the size of a component. In re Rose, 105 USPQ 237 (CCPA 1955). Please note that in the instant application, (see Applicant’s Specification pp. 21-22, [73-75]) Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 18, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein among the plurality of insulation layers (310,320,330), an insulation layer (e.g. 312) positioned at a center (see Fig 4; note that the structural limits of the claimed center are not defined nor a datum of reference claimed) with respect to a stacking direction of the printed circuit board comprises the second insulator (310).
Regarding Claim 20, Kim in view of Lee teaches the limitations of the preceding claim and Kim further teaches the electronic device (Fig 4) of claim 13, wherein the at least one second insulation layer (310) has a thickness of 20 μm or more ([0121]).
Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Ito (US 2019/0214321 A1) in view of Lee (US 2020/0042125 A1).
Regarding Claim 21, Ito discloses an electronic device (Fig 1), comprising: and a printed circuit board (1) and including an alternately stacked plurality of insulation layers (410,51,52) and plurality of conductive layers (3,9), wherein the plurality of insulation layers include at least one first insulation layer (410) and at least two second insulation layers (51,52,8), wherein the at least one first insulation layer (410) includes a first insulator including a resin and a filler ([0039]) having a content of 50% to 70% ([0036-0039]; e.g. 200 parts by mass of filler /300 parts by mass of filler and resin), wherein the at least two second insulation layers (51,52), each of the second insulation layers including a second insulator including a glass fiber (8; [0043]), and wherein the at least one first insulation layer (410) is between each of the second insulation layers (51,52,8).
Ito does not disclose a housing; and a printed circuit board disposed in the housing.
Lee (US 2020/0042125 A1) teaches of an electronic device (Fig 1-2), comprising: a housing (1; see structure 1 shown at least partially housing circuit board 90; [0070]); and a printed circuit board (90) disposed in the housing (1).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Ito, comprising: a housing and a printed circuit board disposed in the housing as taught by Lee, in order to provide a user interface allowing input means and protection (Lee, [0003-0009,0080,0096]) and furthermore a housing would provide environmental protection of the circuit board (Lee, [0003-0009,0080,0096]). Note that the claim has not structurally defined the housing.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROSHN K VARGHESE/ Primary Examiner, Art Unit 2847
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