DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I (Fig. 2), Sub-species A (Fig. 3A) (claims 1, 3, 6-7, 10-14, 17-18) in the reply filed on 06/10/2021 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Furthermore claims 3, 10-11, 17-18 do not read on elected sub-species of Fig. 3A and therefore withdrawn from consideration.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 6-7, 12-14 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 defines “a first redistribution dielectric layer on the first redistribution pattern” is indefinite in view of what’s been defined/labeled in the specification Fig. 2 as a first redistribution dielectric layer IL1 is not on the first redistribution pattern RP1. Appropriate correction is required
Claim 6 defines “a second redistribution pattern comprising:
a via portion penetrating the first redistribution dielectric layer..” is indefinite. As shown in Fig. 2, a second redistribution pattern RP2 via portion penetrating the second redistribution dielectric layer IL2. Appropriate correction is required
Claim 7 defines “wherein the first semiconductor die further comprises:
a second redistribution pattern comprising:
a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and
a pad portion on the first redistribution dielectric layer; and
a conductive pattern on the second redistribution pattern, wherein an upper surface of the first dam has a first height in a height direction from an upper surface of the first substrate” is not aligned with what’s been disclosed/labeled in the specification. As shown in Fig. 3A and defined in the specification, the first redistribution pattern RP1 comprises the claimed elements, not the RP2. Appropriate correction is required
Claim 12 defines “wherein the first dam and the first redistribution dielectric layer DL1 comprise a same material” is indefinite as the specification defines the first dam DM1 may be formed with the same PID as the second redistribution dielectric layer IL2. Appropriate correction is required.
Claims 6-7, 12-14 are also rejected being dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 12 are rejected under 35 U.S.C. 103 as being obvious over Tsai et al (TW 201417223 A) in view of Capote et al (US 2002/0031868 A1).
Regarding claim 1: Tsai teaches in Fig. 8, 12 about a semiconductor package comprising:
PNG
media_image1.png
374
650
media_image1.png
Greyscale
a first semiconductor die 102;
a first under-fill layer 124 on an upper surface of the first semiconductor die;
a second under-fill layer on the first under-fill layer;
a second semiconductor die 120 on the second under-fill layer; and
a mold layer 152 on side surfaces of the second semiconductor die, side surfaces of the second under-fill layer, and the upper surface of the first semiconductor die,
wherein the first semiconductor die comprises:
a first substrate (page 1 teaches semiconductor substrate 102, Fig. 8);
a first redistribution pattern 118 on the first substrate (Fig. 8);
a first redistribution dielectric layer (one or more layers of 116 of Fig. 8 or 132 of Fig. 10) on the first redistribution pattern; and
a first dam 106 on the first redistribution dielectric layer and an edge of the first substrate (as shown), and
wherein the first under-fill layer contacts a side surface of the first dam (Figs. 10, 11, 12).
Tsai does not teach a second under-fill layer on the first under-fill layer;
a second semiconductor die on the second under-fill layer.
Capote teaches in Fig. 10-12 about a first semiconductor die 101;
a first under-fill layer 110 on an upper surface of the first semiconductor die;
a second under-fill layer 112 on the first under-fill layer 110;
a second semiconductor die 100 on the second under-fill layer 112;
PNG
media_image2.png
688
662
media_image2.png
Greyscale
Therefore it would have been obvious to one of ordinary skill in the art, at the time of application was filed to have multilayer underfill layers and thereby having the encapsulants are essentially completely free of entrapped gas bubbles or voids that can lead to increased fatigue on the solder interconnections 102 during subsequent thermal cycling (Capote, page 5)
Regarding claim 6: Capote teaches in Fig. 10-12 depending on what states of the joining process and curing, wherein the first semiconductor die 101 has a first width in a width direction,
wherein the first under-fill layer 109 has a second width in the width direction that is less than the first width,
wherein the second under-fill layer 107 has a third width in the width direction that is less than the second width, and
wherein the second semiconductor die 100 has a fourth width in the width direction that is less than the third width.
PNG
media_image3.png
425
718
media_image3.png
Greyscale
Regarding claim 12: Tsai and Capote teaches wherein the first dam (Capote teaches element 106 that prevents underfill material flow can comprise a metal, an insulator, an epoxy, a polymer, a multilayer structure as described above, or a combination of the foregoing) and the first redistribution dielectric layer comprise a same material (insulating material).
It would have been obvious to one of ordinary skill in the art at the time of the application was filed to have the material as claimed, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 7, 13-14 are rejected under 35 U.S.C. 103 as being obvious over Tsai et al (TW 201417223 A) in view of Capote et al (US 2002/0031868 A1) and further in view of Chen et al. (US PGPUB 2024/0071849 A1)
Regarding claim 7: Capote teaches in Fig. 12 further comprising an internal connection member 102 in the second under-fill layer 112 and connecting the first semiconductor die 101 to the second semiconductor die 100,
wherein the first semiconductor die further comprises:
a second redistribution pattern comprising:
a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and
a pad portion on the first redistribution dielectric layer; and
a conductive pattern on the second redistribution pattern, wherein an upper surface of the first dam has a first height in a height direction from an upper surface of the first substrate (Height of dam 106/110, 134 in Fig. 10, 11, 12 of Capote which are above 132 and redistribution structures are within 132 including any conductive pattern),
wherein an upper surface of the conductive pattern has a second height in the height direction from the upper surface of the first substrate,
wherein the second height is lower than the first height (having the conductive pattern inside 132 of Capote’s Fig. 10, the second height of the conductive pattern would be lower than the dam height) and
wherein an upper sidewall of the first dam is not covered with the first under-fill layer (Capote, Fig. 10, 11, 12).
Tsai in view of Capote does not explicitly talk about wherein the first semiconductor die further comprises:
a second redistribution pattern comprising:
a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and
a pad portion on the first redistribution dielectric layer; and
a conductive pattern on the second redistribution pattern, wherein an upper surface of the first dam has a first height in a height direction from an upper surface of the first substrate
Chen teaches in Fig. 16A (as marked below) a second redistribution pattern comprising:
a via portion penetrating the first redistribution dielectric layer and contacting the first redistribution pattern; and
a pad portion on the first redistribution dielectric layer; and
a conductive pattern on the second redistribution pattern, wherein an upper surface of the first dam has a first height in a height direction from an upper surface of the first substrate.
PNG
media_image4.png
683
1032
media_image4.png
Greyscale
Therefore it would have been obvious to one of ordinary skill in the art, at the time of application was filed to have the feature as claimed of the known UBM structure electrical connectors as well known in the art according to the teachings of Chen to provide electrical connection in packages components (Chen, [0023])
Regarding claims 13-14: As explained above in claims 1, 6-7, Tsai in view of Capote and Chen teaches all the limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Prosecution Insights