DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the stacked memory chip stacks" in lines 2-3 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-2, 8-9, and 15-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al. (US PGPub 20250022787 A1; hereinafter referred to as "Chung”).
Re claim 1: Chung teaches a semiconductor device (FIG. 2: el. 1000; para. 38) comprising: a process chip (FIG. 2: el. 200: para. 39) comprising a process chip frontside back-end-of-the-line (BEOL) interconnect structure (FIG. 3B: el. 234: para. 72) located on a first side of a combined front-end-of-the-line (FEOL)/middle-of-the-line (MOL) level (FIG. 3B: el. 221, 222, 232, 233; para. 71-72), and a power chip backside power distribution network structure located on a second side of the combined FEOL/MOL level (FIG. 3B: el. 600; para. 41); and a memory chip stack comprising a plurality of memory chips stacked one on top of the other and located above the process chip (FIG. 2: el. ST, 400; para. 44|memory chips 400 stacked to form memory chip stack ST above process chip), wherein each memory chip comprises a semiconductor substrate (FIG. 3B: el. 410; para. 75), a combined memory device/MOL level (FIG. 3B: el. 421; para. 75) located on the semiconductor substrate (FIG. 3B), and a memory frontside BEOL interconnect structure (FIG. 3B: el. 431, 432b; para. 76-77) located on the combined memory device/MOL level (FIG. 3B), wherein a hybrid bonding interface is present between the process chip and the memory chip stack (FIG. 3B; para. 43|hybrid bonding interface at intersection of process chip 200 and memory chip 400).
Re claim 2: Chung teaches the semiconductor device of Claim 1, wherein the memory frontside BEOL interconnect structure of a bottommost memory chip of the memory chip stack (FIG. 3B: el. 431, 432b; para. 76-77) contacts the process chip frontside BEOL interconnect structure at the hybrid bonding interface (FIG. 3B: el. 234, 234t: para. 72, 77).
Re claim 8: Chung teaches the semiconductor device of Claim 1, further comprising process chip electrically conductive through structures extending through the process chip (FIG. 3B: el. 211; para. 50).
Re claim 9: Chung teaches the semiconductor device of Claim 8, further comprising memory chip electrically conductive through structures extending through the memory chip stack (FIG. 3B: el. 411; para. 43).
Re claim 15: Chung teaches the semiconductor device of Claim 1, wherein each memory chip is a dynamic access memory chip (para. 44).
Re claim 16: Chung teaches the semiconductor device of Claim 1, wherein the combined FEOL/and MOL level of the process chip (FIG. 3B: el. 221, 222, 232, 233; para. 71-72) comprises a FEOL device level including logic devices (FIG. 3B: el. 221, 223; para. 70), and a MOL level located on the FEOL device level (FIG. 3B: el. 232; para. 72).
Re claim 17: Chung teaches a semiconductor device (FIG. 2: el. 1000; para. 38) comprising: a process chip (FIG. 2: el. 200: para. 39); and a memory chip stack (FIG. 2: el. ST; para. 44) located above the process chip (FIG. 2), wherein a hybrid bonding interface is present between the process chip and the memory chip stack (FIG. 2, 3B; para. 43|hybrid bonding interface at intersection of process chip 200 and memory chip 400).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chung as applied to claim 1 above, and further in view of Sharma et al. (US PGPub 20200135700 A1; hereinafter referred to as "Sharma”).
Re claim 3: Chung teaches the semiconductor device of Claim 1, wherein a bottommost memory chip of the memory chip stack contacts the process chip frontside BEOL interconnect structure at the hybrid bonding interface. Chung fails to teach the semiconductor device of Claim 1, wherein a bottommost memory chip of the memory chip stack includes a memory chip backside power distribution network structure, and the memory chip backside power distribution network structure contacts the process chip frontside BEOL interconnect structure at the hybrid bonding interface.
In a similar field of endeavor, Sharma teaches a semiconductor device (FIG. 3a; para. 6) comprising a process chip (FIG. 3a: el. 303a; para. 28) and a memory chip stack (FIG. 3a: el. 319a; para. 30|memory chip 319a is bottommost memory chip of memory chip stack) above the process chip. Sharma teaches a semiconductor device, wherein a bottommost memory chip of the memory chip stack (FIG. 3a: el. 319a; para. 30) includes a memory chip backside power distribution network structure (FIG. 3a: el. 316a, FIG. 4b, 4e: el. 416; para. 7, 27, 40|short backside TSVs 316a and 416 form back side power structures on backside of memory substrate 318a and backside of memory substrate 406) and the memory chip backside power distribution network structure contacts the process chip frontside BEOL interconnect structure (FIG. 3A: el. 314a; para. 29|BEOL wiring layers 314a form BEOL interconnect structure) at the hybrid bonding interface (FIG. 3a: el. 316a, 314a).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Chung and Sharma, to enable using the memory chip backside power distribution structure of Sharma in the semiconductor device of Chung, for the well-known benefit of providing additional design freedom and density to active features and signal wiring on the front side of the wafer.
Claims 5-7 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chung as applied to claim 1 above, and further in view of Falola et al. (US PGPub 20200388554 A1; hereinafter referred to as " Falola”).
Re claim 5: Chung fails to directly disclose the semiconductor device of Claim 1, further comprising a packaging substrate attached to the process chip backside power distribution network structure (para. 680|Chung teaches that the connection terminals 680, such as solder balls, of the backside power distribution network 600, are for connection to an external substrate).
In a similar field of endeavor, Falola teaches a semiconductor device (FIG. 1: el. 100) comprising: a die formed of a logic chip, a memory chip, or a combination of logic and memory (FIG. 1: el. 106; para. 17-18), and further comprising a packaging substrate (FIG. 1: el. 102; para. 16) attached to the backside of the die. Falola further teaches that a benefit of bonding a die to a packaging substrate is to enable bonding to other electronic elements such as another IC package or a motherboard (para. 16).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Falola and Chung, to enable using the packaging substrate of Falola in the semiconductor device of Chung, for the benefit of enabling connections to other electronic elements.
Re claim 6: The combination of Chung and Falola teaches the semiconductor device of Claim 5, wherein the packaging substrate is attached to the process chip backside power distribution network structure by solder balls (Falola – FIG. 1: el. 122; para. 17).
Re claim 7: The combination of Chung and Falola of the present embodiment fails to teach the semiconductor device of Claim 6, wherein the solder balls are present in an underfill material layer.
Another embodiment of Falola teaches the use of underfill between a die and a package substrate bonded by interconnects, for the benefit of providing mechanical support to the interconnects and preventing delamination (FIG. 3A: el. 128; para. 32). In combination with the teachings of this embodiment, the combination of Chung and Falola teaches the semiconductor device of Claim 6, wherein the solder balls are present in an underfill material layer (Falola - FIG. 3A: el. 128; para. 32).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of another embodiment of Falola with the teaching of the combination of Chung and Falola, to enable using the underfill of Falola in the semiconductor device of the combination of Chung and Falola, for the benefit of providing mechanical support to the interconnects bonded to the package substrate and to prevent delamination.
Re claim 11: Chung fails to teach the semiconductor device of Claim 1, further comprising a thermal interface material layer located on a topmost surface of the memory chip stack. (Falola - FIG. 1A: el. 104; para. 16).
In a similar field of endeavor, Falola teaches a semiconductor device (FIG. 1: el. 100) comprising: a die formed of a logic chip, a memory chip, or a combination of logic and memory (FIG. 1: el. 106; para. 17-18), and further comprising a packaging substrate (FIG. 1: el. 102; para. 16) attached to the backside of the die, and a packaging lid attached to the topside of the die through a thermal interface material (Falola - FIG. 1A: el. 110, 104; para. 16). Falola further teaches that a benefit of the thermal interface material and packaging lid is to dissipate heat from the die (para. 16). The combination of Chung and Falola teaches the semiconductor device of Claim 1, further comprising a thermal interface material layer located on a topmost surface of the memory chip stack. (Falola - FIG. 1A: el. 104; para. 16).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Falola and Chung, to enable using the thermal interface material of Falola in the semiconductor device of Chung, for the benefit of dissipating heat from the top die of the semiconductor device.
Re claim 12: The combination of Chung and Falola teaches the semiconductor device of Claim 1, further comprising a lid (Falola - FIG. 1A: el. 110; para. 16) contacting a packaging substate (Falola - FIG. 1A: el. 110, 102), wherein the packaging substrate is attached to the process chip backside power distribution network structure (taught by combination of Chung and Falola as per Re claim 5 section) and the lid encloses the process chip and the memory chip stack (Falola - FIG. 1A: el. 110, 102|lid encloses the packaged die).
Re claim 13: The semiconductor device of Claim 12, further comprising an adhesive layer (Falola - FIG. 1A: el. 140; para. 16) located between the lid and the packaging substrate (Falola - FIG. 1A: el. 140, 102, 110).
Re claim 14: The semiconductor device of Claim 12, further comprising a dielectric layer adjacent to the memory chip stack (Chung - FIG. 2: el. 710; para. 46), and an air gap located between the dielectric layer and the lid (Falola - FIG. 1A; para. 31|air gaps exist between edge of die (including dielectric at edge of die as taught by Chung and the lid).
25. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chung as applied to claim 1 above, and further in view of Chung et al. (US PGPub 20250006625 A1; hereinafter referred to as "Chung’625”).
Re claim 10: Chung fails to teach the semiconductor device of Claim 9, wherein the memory chip electrically conductive through structures are in contact with the process chip electrically conductive through structures at the hybrid bonding interface.
In a similar field of endeavor, Chung’625 teaches a semiconductor device comprising a process chip (FIG. 1: el. 410; para. 53-54) and a memory stack (FIG. 1: el. 20; para. 53), wherein the memory chip electrically conductive through structures are in contact with the process chip electrically conductive through structures at the bonding interface (para. 56) for the benefit of forming a direct electrical connection.
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Chung’787 and Chung’625, to enable using the bond interface contact of the electrically conductive through structures of the process and memory chips of Chung’625 in the semiconductor device of Chung’787, for the benefit of a direct electrical connection and the well-known benefit of forming high conductivity through power structures in the stacked device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.G./ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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