DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 16-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, claim 15 being linking claim. Election was made without traverse in the reply filed on 7/21/2026.
Applicant’s election without traverse of Claims 1-14 in the reply filed on 7/21/2026 is acknowledged. Claim 15 being linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aichinger, US 2017/0103894.
Regarding claim 1, Aichinger discloses; A vertical power semiconductor device, comprising: a silicon carbide (SiC) semiconductor body including a trench structure extending into the SiC semiconductor body at a first surface of the SiC semiconductor body (Fig. 7A and [0093]; trench gate structures 150 extending from a first surface 101 into a semiconductor body 100 of SiC semiconductor device 500), wherein the trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body (Fig. 7A and [0101]; trench gate structures 150 include the gate electrode 155 and the gate dielectric 151); an interlayer dielectric structure on the trench structure (Fig. 7A and [0111]; interlayer dielectric 210 sandwiched between the first load electrode 310 and the gate electrode 155), wherein the interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer (Fig. 7A and [0111]; interlayer dielectric 210 include one or more dielectric layers from silicon nitride); and a source or emitter electrode on the interlayer dielectric structure (Fig. 7A and [0108]; first load electrode 310 electrically connected or coupled to a first load terminal, which may be an anode terminal of an MCD, a source terminal S of an UMOSFET or an emitter terminal of an IGBT).
Regarding claim 2, Aichinger discloses; the interlayer dielectric structure is predominantly formed by or consists of the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer (Fig. 7A and [0111]; interlayer dielectric 210 include one or more dielectric layers from silicon nitride).
Regarding claim 3, Aichinger discloses; a bottom side of the interlayer dielectric structure directly adjoins to each of the first surface of the SiC semiconductor body, the gate dielectric, and the gate electrode (Fig. 7A ; interlayer dielectric 210 directly adjoins to the first surface 101 of the SiC semiconductor body 100 and the gate electrode 155 and the gate dielectric 151).
Regarding claim 4, Aichinger discloses; a top side of the interlayer dielectric structure directly adjoins to the source or emitter electrode (Fig. 7A; top side of the interlayer dielectric 210 directly adjoins to the first load electrode 310).
Regarding claim 5, Aichinger discloses; the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer directly adjoins to the gate dielectric (Fig. 7A ; layers from silicon nitride of the interlayer dielectric 210 directly adjoins to the gate dielectric 151).
Regarding claim 13, Aichinger discloses; a channel region adjoining to a first sidewall of the trench structure (Fig. 7A and [0110]; minority charge carriers in the body zones 115 form inversion channels connecting the source zones 110 with the drift structure 120); and a diode region adjoining to a second sidewall and to a bottom side of the trench structure, the second sidewall being opposite to the first sidewall (Fig. 7A and [0110] n-doped source zones 110, contact zones 117 and p-doped source zones 110).
Regarding claim 15, Aichinger discloses; A method of manufacturing a vertical power semiconductor device, the method comprising: forming a trench structure in a silicon carbide (SiC) semiconductor body at a first surface of the SiC semiconductor body (Fig. 7A and [0093]; trench gate structures 150 extending from a first surface 101 into a semiconductor body 100 of SiC semiconductor device 500), wherein the trench structure includes a gate electrode and a gate dielectric arranged between the gate electrode and the SiC semiconductor body (Fig. 7A and [0101]; trench gate structures 150 include the gate electrode 155 and the gate dielectric 151); forming an interlayer dielectric structure on the trench structure (Fig. 7A and [0111]; interlayer dielectric 210 sandwiched between the first load electrode 310 and the gate electrode 155), wherein the interlayer dielectric structure includes at least one of an aluminum nitride layer, a silicon nitride layer, an aluminum oxide layer, or a boron nitride layer (Fig. 7A and [0111]; interlayer dielectric 210 include one or more dielectric layers from silicon nitride); and forming a source or emitter electrode on the interlayer dielectric structure (Fig. 7A and [0108]; first load electrode 310 electrically connected or coupled to a first load terminal, which may be an anode terminal of an MCD, a source terminal S of an UMOSFET or an emitter terminal of an IGBT).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Aichinger, US 2017/0103894 as applied to claims 1-5, 13 and 15 above, and further in view of Peters, DE- 102019120692.
Regarding claims 6-7, Aichinger substantially discloses the invention including interlayer dielectric 210 include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass but specifically silent about the interlayer dielectric structure further includes a dielectric layer between the trench structure and the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer in claim 6, the dielectric layer is an oxide layer or a nitride layer in claim 7. However, Peters teaches that dielectric layer of oxide film 1332 between the gate electrode 143 and boron nitride layer 1331 (Fig. 6A).
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It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Aichinger by providing the interlayer dielectric structure further includes a dielectric layer between the trench structure and the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer in claim 6, the dielectric layer is an oxide layer or a nitride layer in claim 7, so that a particular novel design of a gate insulation layer of a power semiconductor device that can provide improved thermal performance (abstract).
Regarding claims 9-10, Aichinger substantially discloses the invention including interlayer dielectric 210 include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass but specifically silent about the interlayer dielectric structure further includes a dielectric layer between the source or emitter electrode and the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer in claim 9, the dielectric layer is an oxide layer or a nitride layer in claim 10. However, Peters teaches that a dielectric film layer of oxide film 1333 between the front metallization 11 and the boron nitride layers 1331 (Fig. 6A).
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It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Aichinger by providing the interlayer dielectric structure further includes a dielectric layer between the source or emitter electrode and the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer in claim 9, the dielectric layer is an oxide layer or a nitride layer in claim 10, so that a particular novel design of a gate insulation layer of a power semiconductor device that can provide improved thermal performance (abstract).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Aichinger, US 2017/0103894 as applied to claims 1-5, 13 and 15 above, and further in view of Sundaresan, US 2020/0388695.
Regarding claim 12, Aichinger substantially discloses the invention including interlayer dielectric 210 include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass but specifically silent about a thickness of the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer ranges from 200 nm to 5 µm. However, Sundaresan teaches that an ILD layer 318 comprising 50 nm-1000 nm thick silicon dioxide, silicon nitride, silicon oxynitride layers or a stacked combination thereof is deposited on the wafer (Fig. 3x and [0126]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Aichinger by providing a thickness of the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer ranges from 200 nm to 5 µm, so that the MOSFET device is configured to suppress a false turn-on of the MOSFET device during a switching transition due to lowering of a threshold voltage caused by a body biasing effect [0029].
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Aichinger, US 2017/0103894 as applied to claims 1-5 and 13 above, and further in view of Siemieniec, US 2017/0345905.
Regarding claim 14, Aichinger discloses; a drain or collector electrode over a second surface of the SiC semiconductor body (Fig. 7A and [0108]; the second load electrode 320 electrically connected or coupled to a second load terminal, which a cathode terminal of an MCD, a drain terminal D of an UMOSFET or a collector terminal of an IGBT); and a drift zone in the SiC semiconductor body between the source or emitter electrode and the drain or collector electrode (Fig. 7A and [0105]; the drift structure 120 include a lightly doped drift zone 121), wherein a doping concentration profile of the drift zone is configured for a nominal blocking voltage between the drain or collector electrode and the source or emitter electrode (Fig. 7A and [0095]; a distance between the first surface 101 at the front side and the second surface 102 on the back is related to a nominal blocking voltage the semiconductor device 500). Aichinger substantially discloses the invention including the nominal blocking voltage but specifically silent about the nominal blocking in a range from 300 V to 20 kV. However, Siemieniec teaches that the semiconductor device 500 has a nominal blocking voltage of 600 V or higher [0076]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Aichinger by providing the nominal blocking in a range from 300 V to 20 kV, so that the output capacitance significantly drops with increasing blocking voltage, the increase of C oss is effective to a high degree [0076].
Claims 8 and 11are rejected under 35 U.S.C. 103 as being unpatentable over Aichinger, US 2017/0103894, in view of Peters, DE- 102019120692, as applied to claims 6-7 and 9-10 above, and further in view of Official Notice.
Regarding claims 8 and 11, Aichinger substantially discloses the invention including interlayer dielectric 210 include one or more dielectric layers from silicon oxide, silicon nitride, silicon oxynitride, doped or undoped silicate glass but specifically silent about a ratio of a thickness of the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer to a thickness of the dielectric layer ranges from 2 to 200 in claims 8 and 11. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Aichinger by providing a ratio of a thickness of the at least one of the aluminum nitride layer, the silicon nitride layer, the aluminum oxide layer, or the boron nitride layer to a thickness of the dielectric layer ranges from 2 to 200 in claims 8 and 11, as the examiner taking official notice of facts that the modification as a matter of common knowledge with routine experimentation in the pertinent art, such as Aichinger, US 2023/0352520 teaches that in the gate dielectric structure a thickness of the high-k dielectric layer, by a factor ranging from 2 to 200, larger than each of a first thickness of the first SiO2 layer, or a second thickness of the second SiO2 layer (Fig. 1A-1B and [0030, 0036]). Since it has been held that the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation- MPEP 2144.05.II.A.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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