DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 04/19/2024.
Currently, claims 1-20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statements (IDS) filed on 04/19/2024 and 05/20/2026. The IDS have been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Independent claim 9 recites “upper surfaces of the interconnect structures and the conductive lines substantially coplanar with one another.” According to Figs. 1C-1H and 2C-2H of the present application, metal lines 112 (i.e., conductive lines or interconnect structures) are disposed over the contacts 120 (i.e., interconnect structures or conductive lines), in which none of the drawings shows upper surfaces of the interconnect structures 120 or 112 and the conductive lines 112 or 120 are substantially coplanar with one another as recited in claim 9.
Independent claim 15 recites “trenches horizontally extending between at least some of the conductive interconnects” and “upper boundaries of the conductive material substantially coincident with upper boundaries of the conductive interconnects.” According to Figs. 1C-1H and 2C-2H of the present application, conductive interconnects 120, 122 are formed in the trenches 114, rather than having the trenches 114 horizontally extending between the conductive interconnects 120, 122 as recited in the claim; and the conductive materials 120, 122 of the trenches 114 appear to form the conductive interconnects 120, 122, rather than having upper boundaries of the conductive material 120, 122 substantially coincident with upper boundaries of the conductive interconnects 120, 122 as recited in the claim.
Therefore, the features of claims 9 and 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claim 9 fails to comply with the written description requirement, because a limitation “upper surfaces of the interconnect structures and the conductive lines substantially coplanar with one another, and an outer diameter of the interconnect structures at an elevation of the upper surfaces of the conductive lines is greater than a width of the conductive lines external to the interconnect structures” is not supported by original disclosure. The specification does not describe upper surfaces of the interconnect structures and the conductive lines are coplanar with one another, and that an outer diameter of the interconnect structures is at an elevation of the upper surfaces of the conductive lines.
Independent claim 15 fails to comply with the written description requirement, because limitations “trenches horizontally extending between at least some of the conductive interconnects” and “upper boundaries of the conductive material substantially coincident with upper boundaries of the conductive interconnects” are not supported by original disclosure. The specification does not describe the trenches horizontally extend between at least some of the conductive interconnects, and that upper boundaries of the conductive material are substantially coincident with upper boundaries of the conductive interconnects.
New or amended claims which introduce elements or limitations which are not supported by the as-filed disclosure violate the written description requirement. See, e.g., In re Lukach, 442 F.2d 967, 169 USPQ 795 (CCPA 1971).
Note the dependent claims 10-14 and 16-20 do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 is indefinite, because:
(1) The abbreviation “3D” has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “3D.”
(2) The abbreviation “CMOS” has not been clearly defined in the claim. It is unclear what is necessarily required by the abbreviation “CMOS.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2016/0293484 A1 to Lee et al. (“Lee”).
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Regarding independent claim 1, Lee in Figs. 25-26 teaches an apparatus (Figs. 25-26 & ¶ 177, wiring structure) comprising:
conductive lines 352, 354 (Figs. 25-26, ¶ 178, first via structure 352 and second via structure 354) extending in a horizontal direction (Figs. 25-26); and
interconnect structures 362, 364 (Figs. 25-26, ¶ 178, first line structure 362 and second line structure 364) vertically intersecting the conductive lines 352, 354 (Figs. 25-26) and extending from upper surfaces of the conductive lines 352, 354 (Fig. 26), the upper surfaces of the conductive lines 352, 354 external to the interconnect structures 362, 364 relatively narrower than upper surfaces of the interconnect structures 362, 364 (Fig. 26, ¶ 182, ¶ 184, upper surfaces of first metal pattern 332, 334 of the conductive lines 352, 354 on the sides are external to the structures 362, 364 and narrower than the upper surfaces of the structures 362, 364).
Regarding claim 2, Lee in Figs. 25-26 further teaches the interconnect structures 362, 364 individually exhibit a substantially circular cross-sectional shape (Fig. 25, the conductive lines 352, 354 are in a circular shape; Figs. 25-26, at least portions of the interconnect structures 362, 364 within the conductive lines 352, 354 would be in circular shape, since the structures 362, 364 fill up spaces within the conductive lines 352, 354 that are circular).
Regarding claim 3, Lee in Fig. 26 further teaches liner material 322, 324 (Fig. 26, ¶ 182, ¶ 184, liner pattern 322, 324) adjacent to the conductive lines 352, 354 without being adjacent to central portions of the interconnect structures 362, 364 (Fig. 26, the liner material 322, 324 are right next to and with physical contact with the conductive lines 352, 354 without being directly right next to and with physical contact with the structures 362, 364).
Regarding claim 8, Lee in Fig. 26 further teaches conductive structures 112, 114 (Fig. 26, ¶ 179, first lower wiring 112 and second lower wiring 114) in vertical alignment with at least some of the interconnect structures 362, 364.
Regarding independent claim 9, Lee in Figs. 25-26 teaches a memory device (Figs. 25-26, ¶ 177 & ¶ 262, memory device including wiring structure), comprising:
conductive lines 352, 354 (Figs. 25-26, ¶ 178, first via structure 352 and second via structure 354) extending horizontally through insulative material 120 (Fig. 26, ¶ 179, insulating interlayer 120); and
interconnect structures 362, 364 (Figs. 25-26, ¶ 178, first line structure 362 and second line structure 364) vertically intersecting the conductive lines 352, 354 (Figs. 25-26), upper surfaces of the interconnect structures 362, 364 and the conductive lines 352, 354 substantially coplanar with one another (Fig. 26, ¶ 182, ¶ 184, the first metal pattern 332, 334 of the conductive lines 352, 354 have upper surfaces coplanar with parts of the upper surfaces of the interconnect structures 362, 364), and an outer diameter of the interconnect structures 362, 364 at an elevation of the upper surfaces of the conductive lines 352, 354 (Fig. 26, the structures 362, 364 are at a higher location than parts of the upper surfaces of the conductive lines 352, 354) is greater than a width of the conductive lines 352, 354 external to the interconnect structures 362, 364 (Fig. 26, ¶ 182, ¶ 184, upper surfaces of first metal pattern 332, 334 of the conductive lines 352, 354 on the sides are external to the structures 362, 364 and narrower than the upper surfaces of the structures 362, 364).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Lee.
Regarding claim 4, Lee does not disclose a width of the upper surfaces of each of the conductive lines external to the interconnect structures is between about 5 nm and about 10 nm less than a width of the upper surfaces of the interconnect structures.
However, Lee teaches a general condition in which a width of the upper surfaces of each of the conductive lines 352, 354 external to the interconnect structures 362, 364 is less than a width of the upper surfaces of the interconnect structures 362, 364 (Fig. 26).
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Lee teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of a width of the upper surfaces of each of the conductive lines external to the interconnect structures being between about 5 nm and about 10 nm less than a width of the upper surfaces of the interconnect structures produce unexpected results that are different in kind and not different in degree, said general conditions taught by Lee renders claim 4 obvious.
Regarding claim 7, Lee does not explicitly disclose an aspect ratio of the interconnect structures is between about 3:1 and about 30:1.
However, it would have been obvious to form the aspect ratio within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US 2019/0043868 A1 to Hasnat et al. (“Hasnat”).
Regarding claim 14, Lee teaches the memory device comprises a NAND Flash memory device (¶ 262).
However, Lee does not explicitly disclose the 3D NAND Flash memory device comprising at least one memory array and a CMOS under array (CUA) region within a horizontal area of the at least one memory array.
Hasnat recognizes a need for providing a memory device that can store more bits (¶ 2). Hasnat satisfies the need by providing a 3D NAND Flash memory device (Fig. 3, ¶ 1, ¶ 21-¶ 22, 3D NAND flash memory) comprising at least one memory array 306 (Fig. 3, ¶ 21, array 306) and a CMOS under array (CUA) region (Fig. 3, ¶ 24, control circuitry 304 including CMOS circuitry and therefore is referred to as CMOS under array or CuA) within a horizontal area of the at least one memory array 306 (Fig. 3).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to use the 3D NAND flash memory device taught by Hasnat for the NAND flash memory device taught by Lee, so as to provide a memory device that can store more bits (Hasnat: ¶ 2).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if (i) rewritten in independent form to include all of the limitations of the base claim and any intervening claims or (ii) the objected claim and any intervening claims are fully incorporated into the base claim.
Claim 5 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 5, wherein the conductive lines and the interconnect structures comprise a substantially continuous portion of a single conductive material.
Claim 6 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 6, wherein openings comprising the conductive lines and the interconnect structures lack seed materials.
Claims 10-13 are rejected, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 10 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 10, wherein the insulative material comprises an etch stop material vertically separating a first insulative material and a second insulative material, the etch stop material below a lowermost boundary of the conductive lines.
Claim 11 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 11, wherein conductive material of the interconnect structures is in direct physical contact with the insulative material and additional conductive material of the conductive lines.
Claim 12 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 12, the interconnect structures directly physically contacting the conductive pads and the conductive lines.
Claim 13 would be allowable, because the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 13, a metal nitride material laterally intervening between the insulative material and the conductive lines, the metal nitride material vertically aligned with portions of the interconnect structures.
Claims 15-20 are rejected, but would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
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Regarding independent claim 15, Lee in Figs. 13-14 teaches a NAND Flash memory device (Figs. 1-2, ¶ 134 & ¶ 262, NAND flash memory device including wiring structure), comprising:
conductive interconnects 241, 243 (Fig. 13, ¶ 136, ¶ 140, first via structures 241 and second via structure 243, in which the structures 241 and 243 both include first metal pattern 225) vertically extending through insulative material 120 (Fig. 13, ¶ 136, insulating interlayer 120); and
trenches 207 (Figs. 13-14, ¶ 139, trench 207) horizontally extending between at least some of the conductive interconnects 241, 243, the trenches 207 comprising conductive material 235 (Fig. 13, ¶ 140, second metal pattern 235) adjacent to the insulative material 120, upper boundaries of the conductive material 235 substantially coincident with upper boundaries of the conductive interconnects 241, 243 (Fig. 13, upper boundary of the material 235 is at the same height and coplanar with (i.e., coincident with) the upper boundaries of the first metal pattern 225 included in the via structures 241 and 243).
However, the prior art of record, singularly or in combination, fails to disclose or suggest, in combination with the other claimed elements in claim 15, a width of an uppermost surface of the conductive material external to the conductive interconnects is relatively less than a width of an uppermost surface of the conductive interconnects.
Therefore, independent claim 15 would be allowable.
Claims 16-20 would be allowable, because they depend from the allowable claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2005/0085070 A1 to Park relates to a metal interconnection line in a semiconductor device, which includes plugs, an aluminum layer formed to connect the plugs, and a barrier metal layer formed to cover the side and bottom surfaces of the aluminum layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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