DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 17 August 2026 of Applicants’ amendments in which claims 1, 4, 5, 7, 9-11, and 14-19 are amended and claim 13 is cancelled. The Office withdraws the drawing objections and indefiniteness rejections identified in the Office Communication dated 28 May 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments filed 17 August 2026 have been fully considered but they are not persuasive.
Applicants argue with respect to claim 1 and in the second paragraph of page 11 that “[n]one of the cited prior art discloses more than a single ‘second gate trench wiring portion’ intersecting each ‘first gate trench wiring portion’.” Applicants further argue in the second paragraph of page 12 that “Naito fails to disclose any trenches that intersect with each other.” Claim 1 is rejected for anticipation over the teachings of Naito and recites that “each of the plurality of second gate trench wiring portions has a separate one of the plurality of intersection portions with the first gate trench wiring portion.” During patent examination, the pending claims must be given their broadest reasonable interpretation consistent with the specification. MPEP §2111. As this principle applies to the present circumstance, Naito teaches that each of the plurality of second gate trench wiring portions (42/48) has a separate one of the plurality of intersection portions (intersection of 42, 48) with the first gate trench wiring portion (48/42) {see alternative annotated copies of Naito’s Fig. 5B below}.
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Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 7 recites “the trench bottom region is provided to extend in the different direction from an outer peripheral portion near a first edge of the semiconductor device to the outer peripheral portion near a second edge of the semiconductor device opposite the first edge of the semiconductor device,” which is not illustrated by the drawings. The only drawing illustrating two edges of a semiconductor device is Fig. 1A, which does not illustrate the above-identified subject matter (e.g., a trench bottom region). All other drawings are limited to illustrating features contained entirely with region R of Fig. 1A, which does not include two edges of a semiconductor device.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 5, and 15-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “the trench bottom region is provided in contact with a bottom portion of the plurality of intersection portions,” which is indefinite because the application does not appear to provide support for multiple intersections portions sharing the same bottom. Instead, paragraph [0065] discloses a bottom portion of a single intersection portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “the trench bottom region is provided in contact with a bottom portion of each of the plurality of intersection portions.” Claim 5 is rejected due to its dependence from intermediate claim 4.
Claim 5 recites “the trench bottom region provided in contact with the bottom portion of the plurality of intersection portions is connected to the well region,” which is indefinite because the application does not appear to provide support for multiple intersections portions sharing the same bottom. Instead, paragraph [0065] discloses a bottom portion of a single intersection portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “the trench bottom region provided in contact with the bottom portion of each of the plurality of intersection portions is connected to the well region.”
Claim 15 recites “an end portion of the plurality of second gate trench wiring portions,” which is indefinite because the application does not appear to provide support for multiple second gate trench wiring portions sharing the same end portion. Instead, paragraph [0066] discloses an end portion of a single second gate trench wiring portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “an end portion of each of the plurality of second gate trench wiring portions.”
Claim 16 recites “an end portion of the plurality of second gate trench wiring portions,” which is indefinite because the application does not appear to provide support for multiple second gate trench wiring portions sharing the same end portion. Instead, paragraph [0066] discloses an end portion of a single second gate trench wiring portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “an end portion of each of the plurality of second gate trench wiring portions.”
Claim 17 recites “an end portion of the plurality of second gate trench wiring portions,” which is indefinite because the application does not appear to provide support for multiple second gate trench wiring portions sharing the same end portion. Instead, paragraph [0066] discloses an end portion of a single second gate trench wiring portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “an end portion of each of the plurality of second gate trench wiring portions.”
Claim 18 recites “an end portion of the plurality of second gate trench wiring portions,” which is indefinite because the application does not appear to provide support for multiple second gate trench wiring portions sharing the same end portion. Instead, paragraph [0066] discloses an end portion of a single second gate trench wiring portion. For the purpose of compact prosecution and to better comport with the application, this will be interpreted as “an end portion of each of the plurality of second gate trench wiring portions.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-12, 14-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito (US20180350960A1).
Regarding claim 1, Naito teaches a semiconductor device including an active portion (110) {Fig. 1; [0082]}, comprising:
a drift region (28) of a first conductivity type (N-type) provided in a semiconductor substrate (10) {Fig. 3; [0124]};
a base region (24) of a second conductivity type (P-type) provided above the drift region (28) {Figs. 2, 4; [0103]};
a gate pad (122) provided above the semiconductor substrate (10) {Fig. 1; [0088]};
an emitter electrode (50) provided above the semiconductor substrate (10) {Fig. 4; [0094]};
a gate trench portion (60) provided on a front surface (12) of the semiconductor substrate (10) in the active portion (110) {Figs. 1-3; [0098]}; and
a gate wiring portion (40, 42, 44, 46, 48) for connecting the gate pad (122) and the gate trench portion (60) {Fig. 1; [0086.0088]};
wherein the gate wiring portion (40, 42, 44, 46, 48) has:
a first gate trench wiring portion (48/42) which extends in a predetermined direction (Y-direction) {Fig. 5B; [0117]}; and
a plurality of second gate trench wiring portions (42/48) which extend in a different direction (X-direction) from the first gate trench wiring portion (48/42) and intersect the first gate trench wiring portion (48/42) at a plurality of an intersection portions (intersection of 42, 48) {Fig. 5B; [0117]}; and
the emitter electrode (50) is provided above the plurality of intersection portions (intersection of 42, 48) {Figs. 5A, 5B}, wherein
each of the plurality of second gate trench wiring portions (42/48) has a separate one of the plurality of intersection portions (intersection of 42, 48) with the first gate trench wiring portion (48/42) {see alternative annotated copies of Naito’s Fig. 5B below}.
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Regarding claim 9, Naito teaches the semiconductor device according to claim 1, and Naito further teaches comprising a well region (20) of the second conductivity type (P-type) provided above the drift region (28) {Fig. 5B, [0103]}
wherein in a cross section parallel to a depth direction (Z direction) of the semiconductor substrate (10) the plurality of intersection portions (intersection of 42, 48) are provided inside the well region (20) and have a lower end which is shallower than a lower end of the well region (20).
Regarding claim 10, Naito teaches the semiconductor device according to claim 9, and Naito further teaches wherein the well region (20) is provided to extend from one end (e.g., left end of 42/48 in Fig. 5B) of the plurality of second gate trench wiring portions (42/48) provided in an outer peripheral portion (region A of Fig. 1) of the semiconductor device to another end (e.g., right end of 42/48 in Fig. 5B) of the plurality of second gate trench wiring portions (42/48) provided in the outer peripheral portion (region A of Fig. 1).
Regarding claim 11, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein the active portion (110 pf Fig. 1) has a first active region (region beneath 50-1) and a second active region (region beneath 50-2) {Fig. 4}, and
in a top view, the emitter electrode (50) is provided from the first active region (region beneath 50-1) to the second active region (region beneath 50-2) over (e.g., at a higher level) the plurality of second gate trench wiring portions (42/48) {Figs. 4 and 5A}.
Regarding claim 12, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein the active portion (110 of Fig. 1) has a first active region (e.g., region to left of E in Fig. 5B) and a second active region (e.g., region to right of E in Fig. 5B), and the first gate trench wiring portion (42) is provided to extend from the first active region (e.g., region to left of E in Fig. 5B) to the second active region (e.g., region to right of E in Fig. 5B), and connects a gate trench portion (e.g., leftmost 60) of the first active region (e.g., region to left of E in Fig. 5B) to a gate trench portion (e.g., rightmost 60) of the second active region (e.g., region to right of E in Fig. 5B) {Fig. 5B; [0096]}.
Regarding claim 14, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein a width of the plurality of second gate trench wiring portions (42) is wider than a width of the first gate trench wiring portion (48) {Fig. 5B}.
Regarding claim 15, as interpreted in view of the indefiniteness rejection, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein the gate wiring portion (40, 42, 44, 46, 48) has a gate metal layer (e.g., 46/48) that is provided in an outer peripheral portion (region A of Fig. 1) of the semiconductor device, is connected to an end portion (e.g., right/top end) of each of the plurality of second gate trench wiring portions ([42/48]/[42]) in the outer peripheral portion (region A of Fig. 1), and is formed of metal {[0112, 0180]}.
Regarding claim 16, as interpreted in view of the indefiniteness rejection, Naito as modified by Ikura teaches the semiconductor device according to claim 2, and Naito further teaches wherein the gate wiring portion (40, 42, 44, 46, 48) has a gate metal layer (e.g., 46/48) that is provided in an outer peripheral portion (region A of Fig. 1) of the semiconductor device, is connected to an end portion (e.g., right/top end) of each of the plurality of second gate trench wiring portions ([42/48]/[42]) in the outer peripheral portion (region A of Fig. 1), and is formed of metal {[0112, 0180]}.
Regarding claim 17, as interpreted in view of the indefiniteness rejection, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein the gate wiring portion has a gate runner (46) that is provided in an outer peripheral portion (region A) of the semiconductor device, is connected to an end portion of each of the plurality of second gate trench wiring portions (42/48) in the outer peripheral portion (region A), and is formed of polysilicon {Figs. 2, 5B; [0112]}.
Regarding claim 18, as interpreted in view of the indefiniteness rejection, Naito teaches the semiconductor device according to claim 1, and Naito further teaches wherein the gate wiring portion (40, 42, 44, 46, 48) has a third gate trench wiring portion (e.g., rightmost 48, whereas first gate trench wiring portion is leftmost 48) that is provided in an outer peripheral portion (region A) of the semiconductor device and is connected to an end portion of each of the plurality of second gate trench wiring portions (42) in the outer peripheral portion (region A) {Fig. 5B}.
Regarding claim 20, Naito teaches the semiconductor device according to claim 1, and Naito further teaches comprising an emitter region (22) which is provided above the drift region 28) and is of the first conductivity type (N-type) with a higher doping concentration (N+ as compared to N-) than that of the drift region {Fig. 4; [0103]}, wherein the emitter electrode (50) is provided above the emitter region (22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito as applied to claim 1 above, and further in view of Ikura et al. (US20230261095A1).
Regarding claim 2, Naito teaches the semiconductor device according to claim 1, but Naito does not teach comprising a trench bottom region of the second conductivity type provided in contact with a bottom portion of the gate trench portion.
In an analogous art, Ikura teaches in Fig. 2B and paragraph [0096] a trench bottom region (75) of a second conductivity type (p-type) provided in contact with a bottom portion of a gate trench portion (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099].
Regarding claim 3, Naito as modified by Ikura teaches the semiconductor device according to claim 2, but Naito does not teach wherein a doping concentration of the trench bottom region is lower than a doping concentration of the base region.
Ikura teaches in Fig. 2B and paragraph [0097] a doping concentration of the trench bottom region (75) is lower than a doping concentration of a base region (14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device as modified by Ikura based on the further teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099].
Regarding claim 4, as interpreted in view of the indefiniteness rejection, Naito as modified by Ikura teaches the semiconductor device according to claim 2, but Naito does not teach wherein the trench bottom region is provided in contact with a bottom portion of each of the plurality of intersection portions.
As discussed above with respect to intermediate claim 2, Ikura teaches in Fig. 2B and paragraph [0096] a trench bottom region (75) of a second conductivity type (p-type) provided in contact with a bottom portion of a gate trench portion (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099]. A consequence of this modification is that Ikura’s trench bottom region would be provided in contact with a bottom portion of each of Naito’s plurality of intersection portions (intersection of 42, 48).
Regarding claim 7, Naito as modified by Ikura teaches the semiconductor device according to claim 2, but Naito does not teach wherein the trench bottom region is provided to extend in the different direction from an outer peripheral portion near a first edge of the semiconductor device to the outer peripheral portion near a second edge of the semiconductor device opposite the first edge of the semiconductor device.
Ikura teaches in Figs. 2A and 2B a trench bottom region (75) is provided to extend in a direction (x direction) from an outer peripheral portion (region A of Fig. 1) near a first edge (e.g., left edge of left 40) of a semiconductor device (device illustrated by Fig. 2B) to the outer peripheral portion (region A of Fig. 1) near a second edge (edge of 30) of the semiconductor device opposite the first edge of the semiconductor device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099]. Moreover, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Ikura) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 5, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito in view of Ikura as applied to claim 4 (for claim 5) and claim 2 (for claims 6 and 8) above, and further in view of Matsui et al. (US20230071170A1).
Regarding claim 5, as interpreted in view of the indefiniteness rejection, Naito as modified by Ikura teaches the semiconductor device according to claim 4, and Naito further teaches comprising a well region (20) of the second conductivity type (P-type) provided above the drift region (28).
Naito does not teach the trench bottom region provided in contact with the bottom portion of each of the plurality of intersection portions is connected to the well region.
However, as discussed above with respect to intermediate claim 2, Ikura teaches in Fig. 2B and paragraph [0096] a trench bottom region (75) of a second conductivity type (p-type) provided in contact with a bottom portion of a gate trench portion (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099]. A consequence of this modification is that Ikura’s trench bottom region (75) would be provided in contact with a bottom portion of each of Naito’s intersection portions (intersection of 42, 48), as discussed above with respect to intermediate claim 4, and would be further connected to Naito’s well region (20).
Moreover, in an analogous art, Matsui teaches in Fig. 2C and paragraph [0081] a trench bottom region (75) is connected to a well region (11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device as modified by Ikura based on the teachings of Matsui, to achieve the above-identified subject matter, so the electric field concentration on the bottom portion of each trench portion can be reduced. Matsui [0069]. Moreover, all the claimed elements (e.g., trench bottom region, well region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Matsui) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 6, Naito as modified by Ikura teaches the semiconductor device according to claim 2, and Naito further teaches comprising a well region (20) of the second conductivity type (P-type) provided above the drift region (28).
Naito does not teach the trench bottom region is connected to the well region.
However, as discussed above with respect to intermediate claim 2, Ikura teaches in Fig. 2B and paragraph [0096] a trench bottom region (75) of a second conductivity type (p-type) provided in contact with a bottom portion of a gate trench portion (40). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Ikura, to achieve the above-identified subject matter, so: (1) the turn-on characteristic of the transistor section … is improved and (2) the electric field strength in the bottom of the gate trench portion … is relaxed, and the avalanche capability is improved. Ikura [0099]. A consequence of this modification is that Ikura’s trench bottom region (75) would be provided in contact with a bottom portion of Naito’s intersection portion (intersection of 42, 48), as discussed above with respect to intermediate claim 4, and would be further connected to Naito’s well region (20).
Moreover, Matsui teaches in Fig. 2C and paragraph [0081] a trench bottom region (75) is connected to a well region (11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device as modified by Ikura based on the teachings of Matsui, to achieve the above-identified subject matter, so the electric field concentration on the bottom portion of each trench portion can be reduced. Matsui [0069]. Moreover, all the claimed elements (e.g., trench bottom region, well region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Matsui) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 8, Naito as modified by Ikura teaches the semiconductor device according to claim 2, and Naito further teaches comprising a well region (20) of the second conductivity type (P-type) provided above the drift region (28) {Fig. 3; [0103]}.
Naito does not teach the trench bottom region has: a first trench bottom portion; and a second trench bottom region which is provided to be separated from the first trench bottom portion and is connected to the well region.
Matsui teaches a first trench bottom portion (75; Fig. 2B); and a second trench bottom region (75; Fig. 2C) which is provided to be separated (not in same cross section) from the first trench bottom portion (75; Fig. 2B) and is connected to the well region (11; Fig. 2c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device as modified by Ikura based on the teachings of Matsui, to achieve the above-identified subject matter, so the electric field concentration on the bottom portion of each trench portion can be reduced. Matsui [0069]. Moreover, all the claimed elements (e.g., trench bottom region, well region) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Matsui) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito as applied to claim 1 above, and further in view of Konishi et al. (US20220157976A1).
Regarding claim 19, Naito teaches the semiconductor device according to claim 1, but Naito does not teach comprising a plated film provided on the emitter electrode above the plurality of intersection portions.
In an analogous art, Konishi teaches in Fig. 1 and paragraph [0077] a plated film (Ni) provided on an emitter electrode (1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Naito’s semiconductor device based on the teachings of Konishi, to achieve the above-identified subject matter, so heat capacity of the emitter electrode … can be increased to improve thermal resistance. Konishi [0091]. Moreover, all the claimed elements (e.g., plated film, emitter electrode) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Konishi) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. A consequence of providing a plated film on Naito’s emitter electrode, which is above the plurality of intersection portions, is that the plated film will also be above the plurality of intersection portions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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