DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement(s) submitted on April 29, 2024 and April 20, 2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0283796 A1 (hereinafter “Udrea”).
Regarding claim 1, Udrea discloses in Figs. 6-8 and related text a semiconductor device (1; [0038]) comprising:
a semiconductor substrate (2, 3, 4, 5, 6, 7, 8; [0038]) having an upper surface and a lower surface and provided with a drift region (5; [0038]) of a first conductivity type (n-type);
an emitter region (7; [0038]) of the first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a higher doping concentration than the drift region (the emitter region 7 is indicated as n+, signifying heavily doped n-type, whereas the drift region 5 is indicated as n-, signifying lightly doped n-type);
a base region (6; [0038]) of a second conductivity type (p-type) provided in contact with the emitter region;
a collector region (2; [0038]) of the second conductivity type provided between the drift region and the lower surface of the semiconductor substrate; and
a floating region (3; [0038], [0040], [0042] and Abstract, lines 15-20) of the first conductivity type provided in contact with an upper surface of the collector region and having a higher doping concentration than the collector region ([0039]), wherein
the collector region has a first region which is not covered with the floating region and a second region which is covered with the floating region.
Regarding claim 6, Udrea discloses a buffer region (4; Fig. 6; [0038]) formed between the collector region and the drift region and having a higher doping concentration than the drift region (the buffer region 4 is indicated as n, signifying moderately doped n-type, whereas the drift region 5 is indicated as n-, signifying lightly doped n-type), wherein
the floating region is arranged between the buffer region and the collector region (Fig. 6), and a doping concentration of the floating region is higher than a doping concentration of the buffer region (the floating region 3 is indicated as n+, signifying heavily doped n-type, whereas the buffer region 4 is indicated as n, signifying moderately doped n-type).
Regarding claim 12, Udrea discloses a gate trench portion (9; Fig. 6; [0038]) provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, wherein the first region is provided at a position overlapping the gate trench portion (Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 7, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Udrea.
Regarding claim 2, Udrea discloses the semiconductor device according to claim 1.
Udrea does not explicitly disclose a doping concentration of the floating region is 10 times or more a doping concentration of the collector region.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a doping concentration of the floating region to be 10 times or more a doping concentration of the collector region because the injection efficiency is not set by the doping concentration of the collector region, which can vary significantly from wafer to wafer or from one semiconductor lot to another, but by the layout dimensions of the n+ islands forming the floating region (Udrea: [0043]).
Examiner notes that, according to [0096] of Applicant’s specification, the claimed relationship of “10 times or more” is not critical but merely one of five possibilities.
Regarding claim 3, Udrea discloses the semiconductor device according to claim 1.
Udrea does not explicitly disclose a thickness of the floating region in a depth direction is 0.5 times or more a thickness of the collector region in the depth direction.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a thickness of the floating region in a depth direction to be 0.5 times or more a thickness of the collector region in the depth direction in order to optimize the hole current injection during the on-state of the semiconductor device (Udrea: Fig. 7 and [0041]).
Furthermore, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04(IV)(A).
Examiner notes that, according to [0097] of Applicant’s specification, the claimed relationship of “0.5 times or more” is not critical but merely one of four possibilities.
Regarding claim 4, Udrea discloses the semiconductor device according to claim 1.
Udrea does not explicitly disclose a product of a doping concentration and a thickness in a depth direction of the floating region is 10 times or more a product of a doping concentration and a thickness in the depth direction of the collector region.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a product of a doping concentration and a thickness in a depth direction of the floating region to be 10 times or more a product of a doping concentration and a thickness in the depth direction of the collector region because the injection efficiency is not set by the doping concentration of the collector region, which can vary significantly from wafer to wafer or from one semiconductor lot to another, but by the layout dimensions of the n+ islands forming the floating region (Udrea: [0043]), and in order to optimize the hole current injection during the on-state of the semiconductor device (Udrea: Fig. 7 and [0041]).
Furthermore, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. MPEP 2144.04(IV)(A).
Examiner notes that, according to [0098] of Applicant’s specification, the claimed relationship of “10 times or more” is not critical but merely one of five possibilities.
Regarding claim 5, Udrea discloses the semiconductor device according to claim 1, comprising a transistor portion (Fig. 6; [0038]).
Udrea does not explicitly disclose when an area of the first region and an area of the second region which occupy the collector region in a top view of the transistor portion are respectively represented by S1 and S2, implantation efficiency of the first region is represented by η1, and the implantation efficiency of the second region is represented by η2, average implantation efficiency ηC given by a following expression is 0.1 or more and 0.4 or less: ηC = (S1 × η1 + S2 × η2)/(S1 + S2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, when an area of the first region and an area of the second region which occupy the collector region in a top view of the transistor portion are respectively represented by S1 and S2, implantation efficiency of the first region is represented by η1, and the implantation efficiency of the second region is represented by η2, to obtain an average implantation efficiency ηC given by a following expression of 0.1 or more and 0.4 or less: ηC = (S1 × η1 + S2 × η2)/(S1 + S2) because the geometry/layout dimensions of the discretized n+ layer (i.e., the floating region as claimed) adjust the level of excess charge in the on-state and thus adjust the level of conductivity modulation of the n- drift region, and as a result, the on-state versus switching performance of the semiconductor device (Udrea: [0038]). Different system applications of the device require different trade-offs between the on-state and switching performance. In general, higher operating frequency applications require faster switching and thus less excess charge in the drift region (Udrea: [0040]).
Regarding claim 7, Udrea discloses the semiconductor device according to claim 3, comprising a transistor portion (Fig. 6; [0038]).
Udrea does not explicitly disclose when an area of the first region and an area of the second region which occupy the collector region in a top view of the transistor portion are respectively represented by S1 and S2, an average doping concentration DC of the collector region is given by a following expression by using a doping concentration NA of the collector region in the first region: DC = S1 × NA/(S1 + S2), the doping concentration NA of the collector region in the first region is higher than the average doping concentration DC, a proportion [Symbol font/0x61] of the area S2 of the second region to the area S1 of the first region is given by a following expression: [Symbol font/0x61] = S2/S1, a proportion β is given by a following expression including a doping concentration ND of the floating region: β = (NA/DC - 1) × ND/(ND - NA), and the doping concentration NA of the collector region in the first region is 10-5 times or more and 0.6 times or less the doping concentration ND of the floating region.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, when an area of the first region and an area of the second region which occupy the collector region in a top view of the transistor portion are respectively represented by S1 and S2, an average doping concentration DC of the collector region is given by a following expression by using a doping concentration NA of the collector region in the first region: DC = S1 × NA/(S1 + S2), the doping concentration NA of the collector region in the first region is higher than the average doping concentration DC, a proportion [Symbol font/0x61] of the area S2 of the second region to the area S1 of the first region is given by a following expression: [Symbol font/0x61] = S2/S1, a proportion β is given by a following expression including a doping concentration ND of the floating region: β = (NA/DC - 1) × ND/(ND - NA), and the doping concentration NA of the collector region in the first region is 10-5 times or more and 0.6 times or less the doping concentration ND of the floating region because the injection efficiency is not set by the doping concentration of the collector region, which can vary significantly from wafer to wafer or from one semiconductor lot to another, but by the layout dimensions of the n+ islands forming the floating region (Udrea: [0043]).
Regarding claim 17, Udrea discloses the implantation efficiency η1 of the first region and the implantation efficiency η2 of the second region are ratios of a current density of minority carriers to a total current density ([0040] and [0042]).
Regarding the limitations "the implantation efficiency η1 of the first region and the implantation efficiency η2 of the second region are ratios of a current density of minority carriers to a total current density" these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Furthermore, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danley, 120 USPQ 528, 531 (CCPA 1959). "Apparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). MPEP 2114(II).
Regarding claim 18, Udrea discloses a transistor portion ([0038]), wherein
in the transistor portion,
at least one of a plurality of first regions including the first region or a plurality of second regions including the second region are repeatedly arranged along a repetition direction, and a width (w+s; Fig. 8; [0042]) of at least one of the plurality of first regions or the plurality of second regions repeatedly arranged in the repetition direction is equal to a repetition pitch.
Claim(s) 8, 14, 16, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Udrea in view of US 2020/0373382 A1 (hereinafter “Osaga”).
Regarding claim 8, Udrea discloses the semiconductor device according to claim 1.
Udrea does not disclose a plurality of gate trench portions are arranged along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and one or more first regions including the first region and one or more second regions including the second region are alternately arranged along the array direction.
Osaga teaches in Fig. 6 and related text a plurality of gate trench portions (4, 5a; [0021]) are arranged along an array direction (left-to-right in the cross-sectional view of Fig. 6), each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region (1; [0019]) and in contact with the emitter region (3; [0021]) and the base region (2; [0021]), and
one or more first regions including the first region (where p-type collector layer 7 is not covered by N++-type layer 8) and one or more second regions including the second region (where the p-type collector layer 7 is covered by the N++-type layer 8) are alternately arranged along the array direction ([0020] and [0035]).
Udrea and Osaga are analogous art because they both are directed to insulated gate bipolar transistors (IGBTs) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Udrea with the specified features of Osaga because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange a plurality of gate trench portions along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and to alternately arrange one or more first regions including the first region and one or more second regions including the second region along the array direction, as taught by Osaga, because of advantages of trench gate IGBT such as a high degree of integration and the capability of high current density (Osaga: [0041]).
Regarding claim 14, Udrea discloses the semiconductor device according to claim 12.
Udrea does not disclose a plurality of gate trench portions including the gate trench portion, wherein the first region is arranged at a position overlapping the plurality of gate trench portions.
Osaga teaches in Fig. 6 and related text a plurality of gate trench portions (4, 5a; [0021]) including the gate trench portion, wherein
the first region (where p-type collector layer 7 is not covered by N++-type layer 8; [0020] and [0035]) is arranged at a position overlapping the plurality of gate trench portions.
Udrea and Osaga are analogous art because they both are directed to insulated gate bipolar transistors (IGBTs) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Udrea with the specified features of Osaga because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a plurality of gate trench portions including the gate trench portion, wherein the first region is arranged at a position overlapping the plurality of gate trench portions, as taught by Osaga, because of advantages of trench gate IGBT such as a high degree of integration and the capability of high current density (Osaga: [0041]).
Regarding claim 16, Udrea discloses the semiconductor device according to claim 12, wherein the collector region has a plurality of first regions including the first region (Fig. 6; [0040]).
Udrea does not disclose all of the first regions are arranged at the position overlapping the gate trench portion.
Osaga teaches in Fig. 6 and related text all of the first regions (where p-type collector layer 7 is not covered by N++-type layer 8; [0020] and [0035]) are arranged at the position overlapping the gate trench portion (4, 5a; [0021]).
Udrea and Osaga are analogous art because they both are directed to insulated gate bipolar transistors (IGBTs) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Udrea with the specified features of Osaga because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange all of the first regions at the position overlapping the gate trench portion, as taught by Osaga, in order to reduce electric field intensity near the back surface of the semiconductor substrate at the time of short circuit operation, thereby obtaining an increase in an interruptible current at the time of short circuit operation (Osaga: [0036]).
Regarding claim 19, Udrea discloses the semiconductor device according to claim 2.
Udrea does not disclose a plurality of gate trench portions are arranged along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and one or more first regions including the first region and one or more second regions including the second region are alternately arranged along the array direction.
Osaga teaches in Fig. 6 and related text a plurality of gate trench portions (4, 5a; [0021]) are arranged along an array direction (left-to-right in the cross-sectional view of Fig. 6), each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region (1; [0019]) and in contact with the emitter region (3; [0021]) and the base region (2; [0021]), and
one or more first regions including the first region (where p-type collector layer 7 is not covered by N++-type layer 8) and one or more second regions including the second region (where the p-type collector layer 7 is covered by the N++-type layer 8) are alternately arranged along the array direction ([0020] and [0035]).
Udrea and Osaga are analogous art because they both are directed to insulated gate bipolar transistors (IGBTs) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Udrea with the specified features of Osaga because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange a plurality of gate trench portions along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and to alternately arrange one or more first regions including the first region and one or more second regions including the second region along the array direction, as taught by Osaga, because of advantages of trench gate IGBT such as a high degree of integration and the capability of high current density (Osaga: [0041]).
Regarding claim 20, Udrea discloses the semiconductor device according to claim 3.
Udrea does not disclose a plurality of gate trench portions are arranged along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and one or more first regions including the first region and one or more second regions including the second region are alternately arranged along the array direction.
Osaga teaches in Fig. 6 and related text a plurality of gate trench portions (4, 5a; [0021]) are arranged along an array direction (left-to-right in the cross-sectional view of Fig. 6), each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region (1; [0019]) and in contact with the emitter region (3; [0021]) and the base region (2; [0021]), and
one or more first regions including the first region (where p-type collector layer 7 is not covered by N++-type layer 8) and one or more second regions including the second region (where the p-type collector layer 7 is covered by the N++-type layer 8) are alternately arranged along the array direction ([0020] and [0035]).
Udrea and Osaga are analogous art because they both are directed to insulated gate bipolar transistors (IGBTs) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Udrea with the specified features of Osaga because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange a plurality of gate trench portions along an array direction, each of the plurality of gate trench portions being a gate trench portion provided from the upper surface of the semiconductor substrate to the drift region and in contact with the emitter region and the base region, and to alternately arrange one or more first regions including the first region and one or more second regions including the second region along the array direction, as taught by Osaga, because of advantages of trench gate IGBT such as a high degree of integration and the capability of high current density (Osaga: [0041]).
Allowable Subject Matter
Claims 9-11, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, individually or in combination, does not teach or suggest “a well region of the second conductivity type enclosing the active portion in a top view and provided in contact with the upper surface of the semiconductor substrate; and an edge termination structure portion arranged between the well region and an end side of the semiconductor substrate” and “the edge termination structure portion is provided with the second region and is not provided with the first region” as recited in claim 9, “a contact area ratio in the first region is higher than a contact area ratio in the second region, and the contact area ratio is a proportion of an area of the contact region exposed on an upper surface of one mesa portion of the one or more mesa portions to an area of the one mesa portion” as recited in claim 13, and “a dummy trench portion provided from the upper surface of the semiconductor substrate to the drift region, in contact with the emitter region and the base region, and electrically connected to the emitter electrode” as recited in claim 15. Claims 10 and 11 depend from claim 9 and therefore would be allowable at least by virtue of their dependency.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
Prosecution Insights