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Last updated: October 22, 2026
Application No. 18/641,416

CATALYTIC METAL PLATE IN A METAL-INSULATOR-METAL CAPACITOR AND METHODS OF FORMING THE SAME

Non-Final OA §102§103§112
Filed
Apr 21, 2024
Priority
Oct 30, 2023 — provisional 63/594,042
Examiner
BENTON, CHLOE ELAINE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

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22 currently pending
Career history
26
Total Applications
across all art units
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Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-10 in the reply filed on 7/27/2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 4/1/2025 is in compliance with time for filing requirements of 37 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. Claim Objections Claims 6 and 7 are objected to because of the following informalities: Missing “than” between limitation “a [third/fourth] electronegativity that is greater…” and “…the electronegativity of molybdenum”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1, 4, 6-7, 21-23, 24, 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 4, 6-7, 21-23 recite the limitation “first one” and/or “second one” in relation to the first and second electrodes, this limitation renders the claims indefinite because it is unclear what structural element (i.e., first electrode, second electrode, sides or portions of individual electrodes, sides or portions of both electrodes, etc.), if any, is defined as “one”. For examination purposes, based on broadest reasonable interpretation, the examiner has interpreted this limitation as defining portions of the individual electrodes. The term “predominant” in claims 24 and 28 is a relative term which renders the claims indefinite. The term “predominant” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation "a predominant volume fraction of the dielectric material is in a symmetrical crystal structure" in claims 24 and 28 is rendered indefinite because it is unclear to what degree qualifies as “predominant” given the infinite range of 50%-99. 9 - % . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Müller et al. (US20230189532A1). Regarding Claim 1: Müller discloses a device structure (Fig. 1) comprising: a first electrode (Fig. 7F elements 210/224) overlying a substrate (paragraph 115); a node dielectric (element 124) contacting the first electrode (paragraphs 59-60 and 73-74) and comprising a dielectric material having a dielectric constant greater than 30 (paragraphs 71, 85-92); and a second electrode (elements 206/222) contacting the node dielectric (paragraphs 59-60 and 73-74), wherein a first one of the first electrode and the second electrode comprises a first catalytic metal plate (elements 206/210/222/224) in direct contact with the node dielectric and having a first electronegativity that is not greater than an electronegativity of molybdenum (paragraphs 61-64). Regarding Claim 2: Müller discloses a device structure according to claim 1, wherein a predominant volume fraction of the dielectric material is in a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure (paragraphs 66-69). Regarding Claim 3: Müller discloses a device structure according to claim 2, wherein the predominant volume fraction comprises at least 80% of an entire volume of the node dielectric (paragraphs 39-45 and 66). Regarding Claim 4: Müller discloses a device structure according to claim 1, wherein a second one of the first electrode and the second electrode (Fig. 7F elements 206/210/222/224) comprises a second catalytic metal plate and having a second electronegativity that is not greater than the electronegativity of molybdenum (paragraphs 61-63). Regarding Claim 5: Müller discloses a device structure according to claim 4, wherein the second catalytic metal plate (Fig. 7F elements 206/210/222/224) is in direct contact with the node dielectric (element 124, paragraphs 59-60 and 73-74). Regarding Claim 6: Müller discloses a device structure according to claim 4, wherein said first one of the first electrode and the second electrode (Fig. 7F elements 206/210/222/224) further comprises a first non-catalytic material plate having a third electronegativity that is greater than the electronegativity of molybdenum and spaced from the node dielectric (element 124) by the first catalytic metal plate (paragraphs 73-75). Regarding Claim 7: Müller discloses a device structure according to claim 6, wherein said second one of the first electrode and the second electrode (Fig. 7F elements 206/210/222/224) comprises a second non-catalytic material plate having a fourth electronegativity that is greater than the electronegativity of molybdenum and spaced from the node dielectric (element 124) by the second catalytic metal plate (paragraphs 73-75). Regarding Claim 21: Müller discloses a device structure (Fig. 1) comprising: a first electrode (Fig. 7F elements 210/224) overlying a substrate (paragraph 115); a node dielectric (element 124) contacting the first electrode (paragraphs 59-60 and 73-74) and comprising a dielectric material (paragraphs 71, 85-92); second electrode (elements 206/222) contacting the node dielectric (paragraphs 59-60 and 73-74); and wherein a first one of the first electrode and the second electrode comprises a first catalytic metal plate (elements 206/210/222/224) in contact with the node dielectric (element 124) and having a first electronegativity that is not greater than an electronegativity of molybdenum (paragraphs 61-64), and wherein said first one of the first electrode and the second electrode further comprises a first non-catalytic material plate (elements 206/210/222/224) having a second electronegativity greater than the electronegativity of molybdenum and spaced from the node dielectric (element 124) by the first catalytic metal plate (paragraphs 73-75). Regarding Claim 22: Müller discloses a device structure according to claim 21, wherein a second one of the first electrode and the second electrode comprises a second catalytic metal plate (Figs. 7E-F elements 206/210/222/224) having a third electronegativity that is not greater than the electronegativity of molybdenum (paragraphs 61-64). Regarding Claim 23: Müller discloses a device structure according to claim 22, wherein said second one of the first electrode and the second electrode comprises a second non-catalytic material plate (Figs. 7E-F elements 206/210/222/224) having a fourth electronegativity that is greater than the electronegativity of molybdenum and spaced from the node dielectric (element 124) by the second catalytic metal plate (paragraphs 73-75). Regarding Claim 24: Müller discloses a device structure according to claim 21, wherein a predominant volume fraction of the dielectric material is in a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure (paragraphs 66-69). Regarding Claim 25: Müller discloses a device structure according to claim 21, further comprising a planar passivation dielectric layer (Figs. 7A-7F element 406, paragraphs 79-81 and 104) contacting a bottom surface of the first electrode (elements 210/224); and a conformal passivation dielectric layer (Figs. 7E-7F element 232, paragraph 83) contacting a top surface of the second electrode (elements 206/222) and contacting sidewalls of the first electrode (elements 210/224), the node dielectric (element 124), and the second electrode (paragraphs 72 and 81-83). Regarding Claim 26: Müller discloses a device structure (Fig. 1) comprising: a first electrode (Fig. 7F elements 210/224) overlying a substrate (paragraph 115); a node dielectric (element 124) contacting the first electrode (paragraphs 59-60 and 73-74) and comprising a dielectric material (paragraphs 71, 85-92); second electrode (elements 206/222) contacting the node dielectric (paragraphs 59-60 and 73-74); a first catalytic metal plate (Figs. 3E-F elements 206/210/222/224) having a first electronegativity that is not greater than an electronegativity of molybdenum (paragraphs 61-64); and a second catalytic metal plate (elements 206/210/222/224) having a second electronegativity that is not greater than the electronegativity of molybdenum (paragraphs 61-64), wherein the first electrode comprises the first catalytic metal plate (elements 210/224), and the second electrode comprises the second catalytic metal plate (elements 206/222), and wherein the first catalytic metal plate and the second catalytic metal plate are in contact with the node dielectric (Fig. 3F, paragraphs 59-60). Regarding Claim 27: Müller discloses a device structure according to claim 26, wherein one of the first electrode and the second electrode further comprises a non-catalytic material plate (Figs. 3E-F elements 206/210/222/224) having a third electronegativity that is greater than the electronegativity of molybdenum and spaced from the node dielectric (element 124) by a respective one of the first catalytic metal plate and the second catalytic metal plate (paragraphs 73-75). Regarding Claim 28: Müller discloses a device structure according to claim 26, wherein a predominant volume fraction of the dielectric material is in a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure (paragraphs 66-69). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 8-10, 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Müller et al. (US20230189532A1) in view of Yamazaki et al. (US9673224B2). Regarding Claim 8: Müller discloses a device structure according to claim 1, further comprising a first field effect transistor (Fig. 1 element 110, paragraphs 17-20) located on a top surface of the substrate (paragraph 115) and first metal interconnect structures (Fig. 7F elements 402A and 402B) electrically connecting (paragraphs 103-104) the first field effect transistor [FET] and the first electrode (elements 210/224) but does not explicitly disclose a second field effect transistor located on the top surface of the substrate. Yamazaki, however, discloses an analogous semiconductor device structure (Fig. 1 element 10) comprising: a first field effect transistor (Fig.2A-B element 100) located on a top surface of the substrate (element 111); a second field effect transistor (element 110) located on the top surface of the substrate (paragraph 93); and first metal interconnect structures (elements 131, 162, 133) electrically connecting (paragraph 83) a source/drain region of the first field effect transistor (element 103b, paragraph 177), a gate electrode of the second field effect transistor (element 115, paragraph 105), and a first electrode of a capacitor (elements 130 and 133, paragraphs 76-79 and 109). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Müller further in view of Yamazaki to explicitly include a second field effect transistor located on the top surface of the substrate. Furthermore, wherein the first metal interconnect structures electrically connect a drain/source region of the first FET, a gate electrode of the second FET, and the first electrode because both are directed to analogous capacitor-based semiconductor structures. Doing so allows for an increase in capacitance while improving the overall electrical performance (Yamazaki, paragraphs 2-3 and 79). Regarding Claim 9: Müller and Yamazaki disclose a device structure according to claim 8, wherein Müller further discloses first dielectric material layers (Fig. 7F elements 404/408) embedding the first metal interconnect structures (elements 402A/402B); and a planar passivation dielectric layer (Figs. 7A-7F element 406, paragraphs 79-80 and 104) overlying the first dielectric material layers and contacting a bottom surface of the first electrode (elements 210/224). Regarding Claim 10: Müller and Yamazaki disclose a device structure according to claim 9, wherein Müller further discloses a conformal passivation dielectric layer (Figs. 7E-7F element 232, paragraph 83) contacting a top surface of the second electrode (elements 206/222) and contacting sidewalls of the first electrode (elements 210/224), the node dielectric (element 124), and the second electrode (paragraphs 72 and 81-83). Regarding Claim 29: Müller discloses a device structure according to claim 26, further comprising a first field effect transistor (Fig. 1 element 110, paragraphs 17-20) located on a top surface of the substrate (paragraph 115) and first metal interconnect structures (Fig. 7F elements 402A and 402B) electrically connecting (paragraphs 103-104) the first field effect transistor [FET] and the first electrode (elements 210/224) but does not explicitly disclose a second field effect transistor located on the top surface of the substrate. Yamazaki, however, discloses an analogous semiconductor device structure (Fig. 1 element 10) comprising: a first field effect transistor (Fig.2A-B element 100) located on a top surface of the substrate (element 111); a second field effect transistor (element 110) located on the top surface of the substrate (paragraph 93); and first metal interconnect structures (elements 131, 162, 133) electrically connecting (paragraph 83) a source/drain region of the first field effect transistor (element 103b, paragraph 177), a gate electrode of the second field effect transistor (element 115, paragraph 105), and a first electrode of a capacitor (elements 130 and 133, paragraphs 76-79 and 109). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Müller further in view of Yamazaki to explicitly include a second field effect transistor located on the top surface of the substrate. Furthermore, wherein the first metal interconnect structures electrically connect a drain/source region of the first FET, a gate electrode of the second FET, and the first electrode because both are directed to analogous capacitor-based semiconductor structures. Doing so allows for an increase in capacitance while improving the overall electrical performance (Yamazaki, paragraphs 2-3 and 79). Regarding Claim 30: Müller and Yamazaki disclose a device structure according to claim 29, but Müller does not explicitly disclose where second metal interconnect structures (Fig. 3F elements 402D and 402E) electrically connect a second electrode to electrical ground. Yamazaki, however, discloses an analogous semiconductor device structure (Fig. 1 element 10) further comprising second metal interconnect structures (elements 31/32, paragraph 66) electrically connecting the second electrode (Fig. 37 elements 1209/1210) to electrical ground (paragraphs 468-471). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Müller further in view of Yamazaki to explicitly include second metal interconnect structures electrically connecting the second electrode to electrical ground because both are directed to analogous capacitor-based semiconductor structures. Doing so improves the overall electrical performance (Yamazaki, paragraphs 2-3 and 481-482). Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Park et al. (US 20230022629 A1), Na et al. (US 20220238634 A1), Lee et al. (US 20220238633 A1), Sakata et al. (US 9171840 B2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899 /Chloë E Benton/Examiner, Art Unit 2899
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Prosecution Timeline

Apr 21, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
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