DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0059108 filed in Ministry of Intellectual Property (MOIP) on May 8, 2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 22, 2024 and IDS filed on November 14, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 15, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. US 2022/0336330 (Kim ‘330).
Regarding claim 15, Kim ‘330 teaches a semiconductor device (e.g., Figs. 1-3 and the description thereof) comprising:
a substrate (e.g., 101, 102 and 105, Fig. 2) comprising an active region (e.g., 102 and 105, Fig. 2) extending in a first direction (e.g., X direction, Fig. 2; Fig. 1);
a gate structure (e.g., GS, Fig. 2, Fig. 1) on the active region, intersecting the active region and extending in a second direction (e.g., Y direction, Fig. 2, Fig. 1);
a source/drain region (e.g., 110, Fig. 2, Fig. 1) adjacent the gate structure and on the active region;
a contact plug (e.g., 180, Fig. 2, Fig. 1) on the source/drain region and electrically connected to the source/drain region (e.g., Fig. 2);
a first power structure (e.g., 120 and a portion of 255 in the A1 region, connected to ML2, Fig. 2, Fig. 3; [59], [55], [53]) on one side of the source/drain region in the second direction and electrically connected to the contact plug; and
a second power structure (e.g., a portion of 255 below the A1 region, connected to ML2, Fig. 2; [59], [55], [53]) penetrating the substrate and on a lower end of the first power structure,
wherein the first power structure and the second power structure are integrated as a unitary structure (e.g., Fig. 2, Fig. 3, [59]), and
the first power structure has a first width (e.g. first width of the upper end of 120, Fig. 2) at an upper end thereof and a second width (e.g. second width of the lower end of the portion of 255 in the A1 region, Fig. 2) at the lower end thereof, and the second width is equal to or greater than the first width (e.g., Fig. 2).
Regarding claim 19, Kim ‘330 teaches a semiconductor device (e.g., Figs. 1-2 and the description thereof) comprising:
a substrate (e.g., 101, 102 and 105, Fig. 2) comprising an active region (e.g., 102 and 105, Fig. 2) extending in a first direction (e.g., X direction, Fig. 2; Fig. 1);
a gate structure (e.g., GS, Fig. 2, Fig. 1) on the active region, intersecting the active region and extending in a second direction (e.g., Y direction, Fig. 2, Fig. 1);
a source/drain region (e.g., 110, Fig. 2, Fig. 1) adjacent the gate structure and on the active region;
a contact plug (e.g., 180, Fig. 2, Fig. 1) on the source/drain region and electrically connected to the source/drain region (e.g., Fig. 2); and
a power structure (e.g., 120 and 255, connected to ML2, Fig. 2, Fig. 3; [59], [55], [53]) on one side of the source/drain region in the second direction, extending in a third direction (e.g., Z direction, Fig. 2, Fig. 1) that is perpendicular to the first and second directions, electrically connected to the contact plug, and penetrating the substrate (e.g., Fig. 2),
wherein the power structure has a first width (e.g. first width of the upper end of 120, Fig. 2) at an upper end thereof and a second width (e.g. second width of the lower end of 255, Fig. 2) at a lower end thereof, and the second width is greater than the first width (e.g., Fig. 2).
Regarding claim 20, Kim ‘330 teaches the semiconductor device of claim 19, wherein the power structure comprises an upper first power structure (e.g., 120, Fig. 2) having a side surface with a first slope and a lower second power structure (e.g., 255, Fig. 2) having a side surface with a second slope that is different from the first slope (e.g., Fig. 2).
Claim 19 is rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Kim et al. US 2020/0373331 (Kim ‘331).
Regarding claim 19, Kim ‘331 teaches semiconductor device (e.g., Figs. 1A-1C and the description thereof) comprising:
a substrate (e.g., 105, 110 and FA, Fig. 1B) comprising an active region (e.g., 110 and FA, Fig. 1B) extending in a first direction (e.g., Y direction, Fig. 1B, Fig. 1A);
a gate structure (e.g., GS, Fig. 1C, Fig. 1A) on the active region, intersecting the active region and extending in a second direction (e.g., X direction, Fig. 1C, Fig. 1A);
a source/drain region (e.g., 130, Fig. 1A, Fig. 19D) adjacent the gate structure and on the active region;
a contact plug (e.g., CP1, Fig. 1B) on the source/drain region and electrically connected to the source/drain region; and
a power structure (e.g., 150 and 160, Fig. 1B, Fig. 1A; [32]) on one side of the source/drain region in the second direction, extending in a third direction (e.g., Z direction, Fig. 1B) that is perpendicular to the first and second directions, electrically connected to the contact plug, and penetrating the substrate (e.g., Fig. 1B),
wherein the power structure has a first width (e.g. first width of the upper end of 150, Fig. 1B) at an upper end thereof and a second width (e.g. second width of the lower end of 160, Fig. 2) at a lower end thereof, and the second width is greater than the first width.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11-14 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. US 2023/0094466 in view of Kim et al. US 2020/0373331 (Kim ‘331).
Regarding claim 1, Frougier teaches a semiconductor device (e.g., Fig. 2, Figs. 18-19 and the description thereof) comprising:
a substrate (e.g., 305, Figs. 18-19) comprising active regions (e.g., upper portions of 305 including fin portions, Figs. 18-19), extending in a first direction (e.g., first direction along the line X, Fig.18; Fig. 2);
a device isolation layer (e.g., 329, 327 and 325, Figs. 18-19) in the substrate between the active regions and exposing upper surfaces of the active regions (e.g., Figs. 18-19);
gate structures (e.g., 1803, Fig. 18; also see Fig. 2 depicting the gates 205 that pertain to the gate stacks 1803) on the active regions, intersecting the active regions and extending in a second direction (e.g., second direction along the line Y, Fig.18; Fig. 2);
source/drain regions (e.g., 355, Figs. 18-19) on the active regions adjacent the gate structures;
contact plugs (e.g., 361, Figs. 18-19) on the source/drain regions, the contact plugs extending into respective recesses in the source/drain regions and electrically connected to the source/drain regions;
a first power structure (e.g., 337, Figs. 18-19) between adjacent source/drain regions of the source/drain regions in the second direction and electrically connected to at least one of the contact plugs (e.g., Figs. 18-19);
a lateral dielectric layer (e.g., 357, Figs. 18-19) on surfaces of the source/drain regions and extending along an upper surface of the device isolation layer and on a first portion of a side surface of the first power structure (e.g., Figs. 18-19),
wherein the first power structure has a first width (e.g., first width of the upper end of 337, Figs. 18-19) at an upper end thereof and a second width (e.g., second width of the lower end of 337, Figs. 18-19) at the lower end thereof, and the second width is equal to or greater than the first width.
Frougier does not explicitly teach a second power structure on a lower end of the first power structure and penetrating the substrate.
Kim ‘331 teaches a second power structure (e.g., 160, Fig. 1B) on a lower end of the first power structure (e.g., 150, Fig. 1B) and penetrating the substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Frougier to include a second power structure on a lower end of the first power structure and penetrating the substrate as suggested by Kim ‘331 for the purpose of stably providing an electrical power to semiconductor devices even down-scaling of the devices for example (e.g., Kim ‘331, [128]).
Regarding claim 11, Frougier in view of Kim ‘331 teaches the semiconductor device of claim 1 as discussed above.
Kim ‘331 further teaches wherein the at least one of the contact plugs is a first contact plug (e.g., CP1, Fig. 1B) between and electrically connected to the adjacent source/drain regions in the second direction (e.g., second direction along the line X1-X1’, Fig 1B). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Frougier to include wherein the at least one of the contact plugs is a first contact plug between and electrically connected to the adjacent source/drain regions in the second direction as suggested by Kim ‘331 for the purpose of reducing contact resistance and increasing device density for example.
Regarding claim 12, Frougier in view of Kim ‘331 teaches the semiconductor device of claim 1, wherein a second portion of the side surface of the first power structure that protrudes beyond the device isolation layer is free of the lateral dielectric layer (e.g., Frougier, Fig. 18).
Regarding claim 13, Frougier in view of Kim ‘331 teaches the semiconductor device of claim 1, wherein a slope of the side surface of the first power structure is substantially equal to a slope of respective side surfaces of the active regions (e.g., Frougier, Figs. 18-19).
Regarding claim 14, Frougier in view of Kim ‘331 teaches the semiconductor device of claim 1, further comprising: a plurality of channel layers (e.g., Frougier, 311, 315, 319, Fig. 18) on the active regions, spaced apart from each other in a third direction (e.g., Frougier, third direction corresponding to the direction along which the channel layers 311, 315 and 319 are arranged, Fig. 18) that is perpendicular to an upper surface of the substrate with portions of the gate structures (e.g., Frougier, 1803, Fig. 18) therebetween.
Claims 1, 4, 6 and 8-14 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. US 2023/0094466 in view of Kim et al. 2022/0336330 (Kim ‘330).
Regarding claim 1, Frougier teaches a semiconductor device (e.g., Fig. 2, Figs. 18-19 and the description thereof) comprising:
a substrate (e.g., 305, Figs. 18-19) comprising active regions (e.g., upper portions of 305 including fin portions, Figs. 18-19), extending in a first direction (e.g., first direction along the line X, Fig.18; Fig. 2);
a device isolation layer (e.g., 329, 327 and 325, Figs. 18-19) in the substrate between the active regions and exposing upper surfaces of the active regions (e.g., Figs. 18-19);
gate structures (e.g., 1803, Fig. 18; also see Fig. 2 depicting the gates 205 that pertain to the gate stacks 1803) on the active regions, intersecting the active regions and extending in a second direction (e.g., second direction along the line Y, Fig.18; Fig. 2);
source/drain regions (e.g., 355, Figs. 18-19) on the active regions adjacent the gate structures;
contact plugs (e.g., 361, Figs. 18-19) on the source/drain regions, the contact plugs extending into respective recesses in the source/drain regions and electrically connected to the source/drain regions;
a first power structure (e.g., 337, Figs. 18-19) between adjacent source/drain regions of the source/drain regions in the second direction and electrically connected to at least one of the contact plugs (e.g., Figs. 18-19);
a lateral dielectric layer (e.g., 357, Figs. 18-19) on surfaces of the source/drain regions and extending along an upper surface of the device isolation layer and on a first portion of a side surface of the first power structure (e.g., Figs. 18-19),
wherein the first power structure has a first width (e.g., first width of the upper end of 337, Figs. 18-19) at an upper end thereof and a second width (e.g., second width of the lower end of 337, Figs. 18-19) at the lower end thereof, and the second width is equal to or greater than the first width.
Frougier does not explicitly teach a second power structure on a lower end of the first power structure and penetrating the substrate.
Kim ‘330 teaches a second power structure (e.g., 255, Fig. 2) on a lower end of the first power structure (e.g., 120, Fig. 2) and penetrating the substrate.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Frougier to include a second power structure on a lower end of the first power structure and penetrating the substrate as suggested by Kim ‘330 for the purpose of lowering contact resistance between buried power structures/rails, thereby reducing unintentional voltage reduction across the structures/rails for example (e.g., Kim ‘330, [120]).
Regarding claim 4, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, wherein the first power structure and the second power structure are a unitary structure (e.g., Kim ‘330, Fig. 2, Fig. 3, [59]).
Regarding claim 6, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1 as discussed above.
Kim ‘330 further teaches wherein the contact plugs respectively comprise a second barrier layer (e.g., 182, Fig. 2) on a lower surface and a side surface thereof, wherein the second barrier layer is on the upper end of the first power structure (e.g., 120, Fig. 2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Frougier to include wherein the contact plugs respectively comprise a second barrier layer on a lower surface and a side surface thereof, wherein the second barrier layer is on the upper end of the first power structure as suggested by Kim ‘330 for the purpose of reducing diffusion of metal atoms of the contact plugs into surrounding insulating layers for example.
Regarding claim 8, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, wherein the second power structure (e.g., Kim ‘330, 255, Fig. 2) has a third width at an upper end thereof and a fourth width at a lower end thereof, the fourth width being greater than the third width (e.g., Kim ‘330, Fig. 2).
Regarding claim 9, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 8, wherein the third width is equal to or greater than the second width (e.g., Kim ‘330, Fig. 2)
Regarding claim 10, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, wherein the second power structure (e.g., Kim ‘330, 255, Fig. 2) and the contact plugs (e.g., Kim ‘330, 180, Fig. 2) comprise respective inclined side surfaces and respective widths that narrow toward an upper surface of the substrate (e.g., Kim ‘330, Fig. 2).
Regarding claim 11, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1 as discussed above.
Kim ‘330 further teaches wherein the at least one of the contact plugs is a first contact plug (e.g., 180, Fig. 2) between and electrically connected to the adjacent source/drain regions in the second direction (e.g., second direction along the line I-I’, Fig. 2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Frougier to include wherein the at least one of the contact plugs is a first contact plug between and electrically connected to the adjacent source/drain regions in the second direction as suggested by Kim ‘330 for the purpose of reducing contact resistance and increasing device density for example.
Regarding claim 12, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, wherein a second portion of the side surface of the first power structure that protrudes beyond the device isolation layer is free of the lateral dielectric layer (e.g., Frougier, Fig. 18).
Regarding claim 13, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, wherein a slope of the side surface of the first power structure is substantially equal to a slope of respective side surfaces of the active regions (e.g., Frougier, Figs. 18-19).
Regarding claim 14, Frougier in view of Kim ‘330 teaches the semiconductor device of claim 1, further comprising: a plurality of channel layers (e.g., Frougier, 311, 315, 319, Fig. 18) on the active regions, spaced apart from each other in a third direction (e.g., Frougier, third direction corresponding to the direction along which the channel layers 311, 315 and 319 are arranged, Fig. 18) that is perpendicular to an upper surface of the substrate with portions of the gate structures (e.g., Frougier, 1803, Fig. 18) therebetween.
Allowable Subject Matter
Claims 2, 3, 5 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention.
For example, Xie et al. US 2022/0223698 and Xie et al. US 2023/0086033 relate to a semiconductor device including a power structure between adjacent source/drain regions and electrically connected to at least one of the contact plugs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 July 23, 2026
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