Prosecution Insights
Last updated: August 01, 2026
Application No. 18/641,739

RESONANT INDUCTIVE-CAPACITIVE ISOLATED DATA CHANNEL

Non-Final OA §102§112
Filed
Apr 22, 2024
Priority
Dec 12, 2020 — divisional of 11/476,189 +1 more
Examiner
GUMEDZOE, PENIEL M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
1099 granted / 1321 resolved
+15.2% vs TC avg
Minimal +4% lift
Without
With
+3.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
19 currently pending
Career history
1334
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
76.4%
+36.4% vs TC avg
§102
12.0%
-28.0% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1321 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 04/22/24 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 11-14 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11 recites “a first metal layer on the first metal layer”. That is indefinite and it is believed Applicants meant to write “a first metal layer on the first dielectric layer”. Claim 20 recites “the bond wire is a second bond wire, and wherein the electronic device further comprises a second bond wire”. The underlined portions are found indefinite because they are different entities being called by the same words, and that is confusing. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Funaya et al. (US 2015/0206934, cited on IDS). a. Re claim 1, Funaya et al. disclose an electronic device, comprising: a substrate SB (for chip CP2; see figs. 3&83-92 and related text; see [0130] and remaining of disclosure for more details); a first dielectric layer IL1&IL2 ([0137]) over the substrate; a first metal layer CL7&HW3&CL8 ([0441], [0458]) on the first dielectric layer, the first metal layer comprising a first plate HW3 (figs. 85-86); a second dielectric layer LF ([0122]) over the first dielectric layer and the first metal layer; a second metal layer CL5&PD5 on the second dielectric layer, the second metal layer comprising: a second plate PD5 (or PD5 and its corresponding layer UM) spaced apart from the first plate; and a winding CL5 around the second plate (figs. 84&86). b. Re claim 8, electronic device of claim 1, further comprises a protective overcoat layer PA (fig. 86, [0162]) over the second dielectric layer and the second metal layer, the protective overcoat layer having an opening OP3 that exposes a portion of the second plate. c. Re claim 9, electronic device of claim 1, further comprises a bond wire BW9 (see fig. 92) coupling the second plate to a chip CP1. Allowable Subject Matter Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 11-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 10 and 15-19 are marked as objected to because of dependent claims 11-14 (for claim 10) and dependent claim 20 (for claims 15-19) being rejected under 112 2nd but would be allowable assuming the 112 2nd issues of claims 11 and 20 are resolved. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Khanolkar et al. (US 2020/0211939) and Larson, III et al. (US 2005/0093659) disclose devices similar to the claimed invention. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 22, 2024
Application Filed
Apr 23, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12696580
GROUP III-NITRIDE EXCITONIC HETEROSTRUCTURES
4y 1m to grant Granted Jul 28, 2026
Patent 12696802
SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
3y 10m to grant Granted Jul 28, 2026
Patent 12690454
Electronic Package and Device Comprising the Same
3y 1m to grant Granted Jul 21, 2026
Patent 12690487
EMBEDDING AN ELECTRONIC COMPONENT IN A CORE OF AN INTEGRATED CIRCUIT SUBSTRATE
3y 1m to grant Granted Jul 21, 2026
Patent 12685155
ELECTRONIC PACKAGE AND SUBSTRATE STRUCTURE THEREOF
2y 11m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
87%
With Interview (+3.6%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1321 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month