Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Rajendran et al. in view of Zhou.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 7, 10, 12, 15-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rajendran et al. (“Fault Analysis-Based Logic Encryption” published in 2015; hereinafter referred to as Rajendran) in view of Zhou (US Pat. Pub. 20190018936).
As per claims 1, 12, and 17:
Rajendran teaches a logic preprocessor to identify a first stuck-at fault for testing with a logic circuit, wherein the first stuck-at fault is associated with a first signal of the logic circuit and a digital logic stuck-at value (Rajendran page 4 sec. 4.2.1, circuit to compute number of patterns that detect a stuck-at-0 fault and compute number of patterns and number of outputs for stuck-at-1 faults);
a lock circuit generator to insert a key gate in the logic circuit at the first stuck-at fault for testing to generate a locked logic circuit, wherein the key gate receives a key value and a value of the first signal associated with the first stuck-at fault (Rajendran pg. 4-5 sec. 4.2.1-4.2.2, insert XOR/XNOR key gates at the location with the highest fault impact, which is related to the stuck-at-faults and the key gates receive key-bits), and wherein when the key value is a first key value the key gate generates the digital logic stuck-at value (Rajendran pg. 4 sec. 4.1, application of a wrong key is associated with the activation of a stuck-at fault), and wherein when the key value is a second key value the key gate propagates the value of the first signal (Rajendran pg. 1 sec. 1.2, valid key is supplied to produce correct outputs, interpreted as propagating values) and identify the first stuck-at fault as a redundant fault in response to a determination that an input test pattern associated with the first stuck-at fault does not exist (Rajendran pg. 4 sec. 4.1, when multiple faults are excited, they mask one another, which is interpreted as redundant faults. Please note this is related to wrong keys being blocked for input patterns as stated in Rajendran pg. 7 section 4.4.2).
Rajendran does not explicitly disclose a computing device for logic circuit test pattern generation, the computing device comprising and a fault analyzer to (i) determine whether an input test pattern associated with the first stuck-at fault exists by performance of a Boolean satisfiability attack on the locked logic circuit. However, Zhou discloses a computing device for logic circuit test pattern generation (Zhou par. 0115-0120, computing system 1200 and a logic circuit design algorithm 1230) and a fault analyzer to (i) determine whether an input test pattern associated with the first stuck-at fault exists by performance of a Boolean satisfiability attack on the locked logic circuit (Zhou par. 0041, performing a Boolean satisfiability-based attack to determine the existence of differentiating input patterns).
Rajendran and Zhou are analogous arts because they are in the same field of endeavor of logic encryption. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Zhou’s Boolean satisfiability-based attack with the stuck-at-faults in the computing device, method, and non-transitory computer-readable medium of Rajendran. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it is known that Boolean-satisfiability-based attacks successfully defeat traditional logic encryption systems (Zhou par. 0022) so they can be used to evaluate the existence of input test patterns associated with stuck-at faults.
As per claim 3:
Rajendran and Zhou further teach the computing device of claim 1, wherein the first stuck-at fault comprises a stuck-at-1 fault or a stuck-at-0 fault (Rajendran pg. 4 sec. 4.2.1).
As per claims 7, 15, and 19:
Rajendran and Zhou further teach the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17, wherein the logic preprocessor is to identify a plurality of stuck-at faults, the plurality of stuck-at faults comprising the first stuck-at fault (Rajendran pg. 4 sec. 4.2.1); the lock circuit generator is to, for each stuck-at fault of the plurality of stuck-at faults, insert a key gate in the logic circuit at the corresponding stuck-at fault to generate a plurality of locked logic circuits (Rajendran pg. 4-5 sec. 4.2.1-4.2.2, inserting a key-gate to create locked logic circuits); and the fault analyzer is to, for each stuck-at fault of the plurality of stuck-at faults, (i) determine whether an input test pattern associated with the corresponding stuck-at fault exists by performance of the Boolean satisfiability attack on each locked logic circuit of the plurality of locked logic circuits (Zhou par. 0041, performing a Boolean satisfiability-based attack to determine the existence of differentiating input patterns, which is interpreted to be used to evaluate the existence of input test patterns associated with stuck-at faults) and (ii) identify the corresponding stuck-at fault as a redundant fault in response to a determination that an input test pattern associated with the corresponding stuck-at fault does not exist (Rajendran pg. 4 sec. 4.1, when multiple faults are excited, they mask one another, which is interpreted as redundant faults. Please note this is related to wrong keys being blocked for input patterns as stated in Rajendran pg. 7 section 4.4.2).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the same fault analysis and key gate insertion technique to multiple stuck-at faults due to a routine duplication of known operations.
As per claims 10, 16, and 20:
Rajendran and Zhou further teach the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17, wherein the logic preprocessor is to identify a plurality of stuck-at faults, the plurality of stuck-at faults comprising the first stuck-at fault (Rajendran pg. 4 sec. 4.2.1); the lock circuit generator is to insert a plurality of key gates in the logic circuit to generate the locked logic circuit wherein each key gate corresponds to a stuck-at fault of the plurality of stuck-at faults (Rajendran pg. 4-5 sec. 4.2.1-4.2.2, inserting key-gates to create a locked logic circuit); and the fault analyzer is to determine an input test pattern associated with each stuck-at fault of the plurality of stuck-at faults that is not a redundant fault by the performance of the Boolean satisfiability attack on the locked logic circuit (Zhou par. 0041, performing a Boolean satisfiability-based attack to determine the existence of differentiating input patterns, which is interpreted to be used to evaluate the existence of input test patterns associated with stuck-at faults).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the same fault analysis and key gate insertion technique to multiple stuck-at faults due to a routine duplication of known operations.
Claims 4-6, 10, 14, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Rajendran-Zhou in further view of Forte et al. (US Pat. Pub. 20200273818; hereinafter referred to as Forte).
As per claim 4:
Rajendran and Zhou teach the computing device of claim 1.
Rajendran and Zhou do not explicitly disclose wherein to insert the key gate in the logic circuit at the first stuck-at fault comprises to insert an AND gate for a stuck-at-1 fault and to insert an OR gate for a stuck-at-0 fault. However, Forte discloses wherein to insert the key gate in the logic circuit at the first stuck-at fault comprises to insert an AND gate for a stuck-at-1 fault and to insert an OR gate for a stuck-at-0 fault (Forte par. 0154-0159, insert either NAND gates for a stuck-at-1 fault or NOR gates for a stuck-at-0 fault. Please note NAND/NOR are universal gates and any AND/OR function can be implemented using NAND/NOR gates, thus the use of AND/OR gates is merely a design choice).
Rajendran, Zhou, and Forte are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Forte’s NAND/NOR gates with the computing device of Rajendran. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for the creation of secure designs that incur significant overhead in terms of area and performance (Forte par. 0005).
As per claim 5:
Rajendran and Zhou teach the computing device of claim 1.
Rajendran and Zhou do not explicitly disclose wherein to insert the key gate in the logic circuit further comprises to insert a buffer at a logic fanout segment in the logic circuit. However, Forte discloses wherein to insert the key gate in the logic circuit further comprises to insert a buffer at a logic fanout segment in the logic circuit (Forte par. 0157, fan-out cone of NOR gate. Please note inserting a buffer at a fanout segment is a routine, obvious location that would occur to any person of ordinary skill in the art, thus inserting a buffer at a logic fanout segment in the logic circuit is merely a design choice).
Rajendran, Zhou, and Forte are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Forte’s insertion of a buffer at a logic fanout segment with the computing device of Rajendran. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for the creation of secure designs that incur significant overhead in terms of area and performance (Forte par. 0005).
As per claims 6, 14, and 18:
Rajendran and Zhou teach the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17.
Rajendran and Zhou do not explicitly disclose further comprising an automatic test pattern generation tool to: perform an automatic test pattern generation process with the logic circuit; and identify a plurality of undetected stuck-at faults in the logic circuit in response to performance of the automatic test pattern generation process; wherein the plurality of undetected stuck-at faults comprises the first stuck-at fault. However, Forte discloses further comprising an automatic test pattern generation tool (Forte par. 0155, ATPG tool) to: perform an automatic test pattern generation process with the logic circuit; and identify a plurality of undetected stuck-at faults in the logic circuit in response to performance of the automatic test pattern generation process; wherein the plurality of undetected stuck-at faults comprises the first stuck-at fault (Forte par. 0160 and Table 6, the results of the ATPG process shows that there are a plurality of not detected stuck-at faults).
Rajendran, Zhou, and Forte are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Forte’s ATPG tool with the computing device, method, and non-transitory computer-readable media of Rajendran. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it allows for the creation of secure designs that incur significant overhead in terms of area and performance (Forte par. 0005).
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable by Rajendran-Zhou in further view of Akita (US Pat. Pub. 20110145664).
As per claims 2 and 13:
Rajendran and Zhou teach the computing device of claim 1 and the method of claim 12.
Rajendran and Zhou do not explicitly disclose a test manager to (i) input the input test pattern associated with the first stuck-at fault to a device under test that comprises the logic circuit and (ii) compare an output pattern received from the logic circuit of the device under test in response to inputting of the input test pattern to an expected output. However, Akita discloses a test manager to (i) input the input test pattern associated with the first stuck-at fault to a device under test that comprises the logic circuit (Akita par. 0017, generates a test pattern to be supplied to device under test 200. Please note it is well-known in the art for ATPG test patterns to generate test patterns to check for faults, and specifically stuck-at faults as stated in Forte par. 0143) and (ii) compare an output pattern received from the logic circuit of the device under test in response to inputting of the input test pattern to an expected output (Akita par. 0017, compare an acquired output pattern output by the device under test to an expected value pattern).
Rajendran, Zhou, and Akita are analogous arts because they are in the same field of endeavor of testing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Akita’s input test pattern from a device under test and compare an outputted test pattern with an expected test pattern with the computing device and method of Rajendran-Zhou. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it can help identify any mismatches between the output pattern and the expected value pattern (Akita par. 0011).
Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable by Rajendran-Zhou in further view of Fujita et al. ("Efficient SAT-based ATPG techniques for all multiple stuck-at faults” published in 2014).
As per claim 8:
Rajendran and Zhou teach the computing device of claim 7.
Rajendran and Zhou do not explicitly disclose wherein to determine whether an input test pattern associated with the corresponding stuck-at fault exists comprises to:
perform an iteration of the Boolean satisfiability attack on the corresponding locked logic circuit; determine whether the corresponding locked logic circuit is satisfiable in response to performance of the iteration of the Boolean satisfiability attack; and
determine that the corresponding stuck-at fault is a redundant fault in response to a determination that the corresponding locked logic circuit is not satisfiable. However, Fujita discloses wherein to determine whether an input test pattern associated with the corresponding stuck-at fault exists comprises to: perform an iteration of the Boolean satisfiability attack on the corresponding locked logic circuit (Fujita pg. 2 col. 2, solving a set of SAT problems); determine whether the corresponding locked logic circuit is satisfiable in response to performance of the iteration of the Boolean satisfiability attack (Fujita Abstract, SAT based formulations for ATPG of circuits have a large number of faults. Please note the satisfiability is checked as seen in Fujita Fig. 3); and determine that the corresponding stuck-at fault is a redundant fault in response to a determination that the corresponding locked logic circuit is not satisfiable (Fujita pg. 4 col. 2, implicitly eliminating all detectable faults. Please note after all detectable faults are eliminated, the remaining faults are the ones that were not satisfiable and are undetected).
Rajendran, Zhou, and Fujita are analogous arts because they are in the same field of endeavor of test patterns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Fujita’s solving a set of SAT problems by implicitly eliminating all detectable faults with the computing device of Rajendran-Zhou. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it makes the solving process more efficient (Fujita Abstract).
As per claim 9:
Rajendran, Zhou, and Fujita further teach the computing device of claim 8 wherein to determine the input test pattern associated with the corresponding stuck-at fault comprises to: determine a distinguishing input pattern for the corresponding locked logic circuit in response to a determination that the corresponding locked logic circuit is satisfiable (Fujita Abstract and Fig. 3, in response to a determination of satisfiability, generate test vectors), wherein the input test pattern comprises the distinguishing input pattern (Fujita pg. 4 col. 1, a set of complete test vectors for all combinations of multiple stuck-at faults which are detectable is generated).
As per claim 11:
Rajendran and Zhou teach the computing device of claim 10.
Rajendran and Zhou do not explicitly disclose wherein to perform the Boolean satisfiability attack comprises to determine a plurality of distinguishing input patterns for the locked logic circuit, wherein the plurality of distinguishing input patterns comprises the input test pattern associated with each stuck-at fault that is not a redundant fault. However, Fujita discloses wherein to perform the Boolean satisfiability attack comprises to determine a plurality of distinguishing input patterns for the locked logic circuit, wherein the plurality of distinguishing input patterns comprises the input test pattern associated with each stuck-at fault that is not a redundant fault (Fujita Abstract and Fig. 3, in response to a determination of satisfiability, also meaning the stuck-at fault is detectable, generate test vectors. Please note a set of complete test vectors for all combinations of multiple stuck-at faults which are detectable is generated as stated in Fujita pg. 4 col. 1).
Conclusion
The additional prior arts made of record and have not been relied upon are
considered pertinent to applicant’s disclosure as follows:
Sinanoglu (US Pat. Pub. 20230177245) discloses a logic-locked integrated circuit that can receive requests and swap a correct key with an incorrect key. Sinanoglu further discloses inserting XOR or XNOR key-gates in locations of the logic locked design.
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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