Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-7, 10, 12-16, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable by Sinanoglu (US Pat. Pub. 20230177245; domestic priority date 05/07/2020) in view of Forte et al. (US Pat. Pub. 20200273818; hereinafter referred to as Forte).
As per claims 1, 12, and 17:
Sinanoglu teaches a computing device, a method, and one or more non-transitory, computer-readable media comprising a plurality of instructions comprising:
a logic preprocessor to identify a first stuck-at fault for testing with a logic circuit, wherein the first stuck-at fault is associated with a first signal of the logic circuit and a digital logic stuck-at value (Sinanoglu par. 0038, test access detection circuitry 110 receives a scan-enable signal and transmits a corrupt signal 112 when the scan-enable signal is HIGH. Please note any fault that corrupts the correct key includes a fault that can be stuck at the opposite value of the key bit as stated in Sinanoglu par. 0051, which demonstrates a stuck-at fault);
a lock circuit generator to insert a key gate in the logic circuit at the first stuck-at fault for testing to generate a locked logic circuit (Sinanoglu par. 0055, a logic-locked design to insert XNOR or XOR gates), wherein the key gate receives a key value and a value of the first signal associated with the first stuck-at fault (Sinanoglu par. 0039, the logic-locked design is driven by either a correct key or incorrect key), and wherein when the key value is a first key value the key gate generates the digital logic stuck-at value (Sinanoglu par. 0042, when the scan-enable signal is received (e.g. HIGH) the design generates an incorrect mode), and wherein when the key value is a second key value the key gate propagates the value of the first signal (Sinanoglu par. 0042, when the scan-enable signal is not received (e.g. LOW) a correct output mode is generated, allowing the propagation of a signal).
Sinanoglu does not explicitly disclose a fault analyzer to (i) determine whether an input test pattern associated with the first stuck-at fault exists by performance of a Boolean satisfiability attack on the locked logic circuit, and (ii) identify the first stuck-at fault as a redundant fault in response to a determination that an input test pattern associated with the first stuck-at fault does not exist. However, Forte discloses a fault analyzer to (i) determine whether an input test pattern associated with the first stuck-at fault exists by performance of a Boolean satisfiability attack on the locked logic circuit (Forte par. 0149 and Table 5, SAT attack algorithm attempts to find a pattern that distinguishes between correct and incorrect keys. Please note the attack targets specific gates related to stuck-at faults as stated in Forte par. 0155-0159), and (ii) identify the first stuck-at fault as a redundant fault in response to a determination that an input test pattern associated with the first stuck-at fault does not exist (Forte par. 0160 and Table 6, the "ATPG untestable" column identifies untestable faults and where it is impossible to generate a pattern).
Sinanoglu and Forte are analogous arts because they are in the same field of endeavor of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Forte’s SAT attack algorithm with the computing device, method, and non-transitory computer-readable medium of Sinanoglu because the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of this combination would have been predictable since the use of an SAT attack algorithm for attacking logic-locked circuits is a standard, well-known technique for analyzing locked circuits.
As per claim 3:
Sinanoglu and Forte further teach the computing device of claim 1, wherein the first stuck-at fault comprises a stuck-at-1 fault or a stuck-at-0 fault (Forte par. 0155-0159, setting either a stuck-at-0 fault or stuck-at-1 fault).
As per claim 4:
Sinanoglu and Forte further teach the computing device of claim 1, wherein to insert the key gate in the logic circuit at the first stuck-at fault comprises to insert an AND gate for a stuck-at-1 fault and to insert an OR gate for a stuck-at-0 fault (Forte par. 0154-0159, insert either NAND gates for a stuck-at-1 fault or NOR gates for a stuck-at-0 fault. Please note NAND/NOR are universal gates and any AND/OR function can be implemented using NAND/NOR gates, thus the use of AND/OR gates is merely a design choice).
As per claim 5:
Sinanoglu and Forte further teach the computing device of claim 1, wherein to insert the key gate in the logic circuit further comprises to insert a buffer at a logic fanout segment in the logic circuit (Forte par. 0157, fan-out cone of NOR gate. Please note inserting a buffer at a fanout segment is a routine, obvious location that would occur to any person of ordinary skill in the art, thus inserting a buffer at a logic fanout segment in the logic circuit is merely a design choice).
As per claims 6, 14, and 18:
Sinanoglu and Forte further teach the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17, further comprising an automatic test pattern generation tool (Forte par. 0155, ATPG tool) to: perform an automatic test pattern generation process with the logic circuit; and identify a plurality of undetected stuck-at faults in the logic circuit in response to performance of the automatic test pattern generation process; wherein the plurality of undetected stuck-at faults comprises the first stuck-at fault (Forte par. 0160 and Table 6, the results of the ATPG process shows that there are a plurality of not detected stuck-at faults).
As per claims 7, 15, and 19:
Sinanoglu and Forte further teach the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17, wherein the logic preprocessor is to identify a plurality of stuck-at faults, the plurality of stuck-at faults comprising the first stuck-at fault (Sinanoglu par. 0038, test access detection circuitry 110 receives a scan-enable signal and transmits a corrupt signal 112 when the scan-enable signal is HIGH. Please note any fault that corrupts the correct key includes a fault that can be stuck at the opposite value of the key bit as stated in Sinanoglu par. 0051, which demonstrates a stuck-at fault); the lock circuit generator is to, for each stuck-at fault of the plurality of stuck-at faults, insert a key gate in the logic circuit at the corresponding stuck-at fault to generate a plurality of locked logic circuits (Sinanoglu par. 0055, a logic-locked design to insert XNOR or XOR gates); and the fault analyzer is to, for each stuck-at fault of the plurality of stuck-at faults, (i) determine whether an input test pattern associated with the corresponding stuck-at fault exists by performance of the Boolean satisfiability attack on each locked logic circuit of the plurality of locked logic circuits (Forte par. 0149 and Table 5, SAT attack algorithm attempts to find a pattern that distinguishes between correct and incorrect keys. Please note the attack targets specific gates related to stuck-at faults as stated in Forte par. 0155-0159) and (ii) identify the corresponding stuck-at fault as a redundant fault in response to a determination that an input test pattern associated with the corresponding stuck-at fault does not exist (Forte par. 0160 and Table 6, the "ATPG untestable" column identifies untestable faults and where it is impossible to generate a pattern).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the same fault analysis and key gate insertion technique to multiple stuck-at faults due to a routine duplication of known operations.
As per claims 10, 16, and 20:
Sinanoglu and Forte further teaches the computing device of claim 1, method of claim 12, and one or more non-transitory computer-readable media of claim 17, wherein the logic preprocessor is to identify a plurality of stuck-at faults, the plurality of stuck-at faults comprising the first stuck-at fault (Sinanoglu par. 0038, test access detection circuitry 110 receives a scan-enable signal and transmits a corrupt signal 112 when the scan-enable signal is HIGH. Please note any fault that corrupts the correct key includes a fault that can be stuck at the opposite value of the key bit as stated in Sinanoglu par. 0051, which demonstrates a stuck-at fault); the lock circuit generator is to insert a plurality of key gates in the logic circuit to generate the locked logic circuit wherein each key gate corresponds to a stuck-at fault of the plurality of stuck-at faults (Forte par. 0154-0159, insert NAND or NOR gates corresponding to either a stuck-at-0 fault or stuck-at-1 fault); and the fault analyzer is to determine an input test pattern associated with each stuck-at fault of the plurality of stuck-at faults that is not a redundant fault by the performance of the Boolean satisfiability attack on the locked logic circuit (Forte par. 0149 and Table 5, SAT attack algorithm attempts to find a pattern that distinguishes between correct and incorrect keys. Please note the attack targets specific gates related to stuck-at faults as stated in Forte par. 0155-0159).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the same fault analysis and key gate insertion technique to multiple stuck-at faults due to a routine duplication of known operations.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable by Sinanoglu in view of Forte in further view of Akita (US Pat. Pub. 20110145664).
As per claims 2 and 13:
Sinanoglu and Forte teach the computing device of claim 1 and the method of claim 12.
Sinanoglu and Forte do not explicitly disclose a test manager to (i) input the input test pattern associated with the first stuck-at fault to a device under test that comprises the logic circuit and (ii) compare an output pattern received from the logic circuit of the device under test in response to inputting of the input test pattern to an expected output. However, Akita discloses a test manager to (i) input the input test pattern associated with the first stuck-at fault to a device under test that comprises the logic circuit (Akita par. 0017, generates a test pattern to be supplied to device under test 200. Please note it is well-known in the art for ATPG test patterns to generate test patterns to check for faults, and specifically stuck-at faults as stated in Forte par. 0143) and (ii) compare an output pattern received from the logic circuit of the device under test in response to inputting of the input test pattern to an expected output (Akita par. 0017, compare an acquired output pattern output by the device under test to an expected value pattern).
Sinanoglu, Forte, and Akita are analogous arts because they are in the same field of endeavor of testing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Akita’s input test pattern from a device under test and compare an outputted test pattern with an expected test pattern with the computing device and method of Sinanoglu-Forte. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it can help identify any mismatches between the output pattern and the expected value pattern (Akita par. 0011).
Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable by Sinanoglu in view of Forte in further view of Fujita et al. ("Efficient SAT-based ATPG techniques for all multiple stuck-at faults” published in 2014).
As per claim 8:
Sinanoglu and Forte teach the computing device of claim 7.
Sinanoglu and forte do not explicitly disclose wherein to determine whether an input test pattern associated with the corresponding stuck-at fault exists comprises to:
perform an iteration of the Boolean satisfiability attack on the corresponding locked logic circuit; determine whether the corresponding locked logic circuit is satisfiable in response to performance of the iteration of the Boolean satisfiability attack; and
determine that the corresponding stuck-at fault is a redundant fault in response to a determination that the corresponding locked logic circuit is not satisfiable. However, Fujita discloses wherein to determine whether an input test pattern associated with the corresponding stuck-at fault exists comprises to: perform an iteration of the Boolean satisfiability attack on the corresponding locked logic circuit (Fujita pg. 2 col. 2, solving a set of SAT problems); determine whether the corresponding locked logic circuit is satisfiable in response to performance of the iteration of the Boolean satisfiability attack (Fujita Abstract, SAT based formulations for ATPG of circuits have a large number of faults. Please note the satisfiability is checked as seen in Fujita Fig. 3); and determine that the corresponding stuck-at fault is a redundant fault in response to a determination that the corresponding locked logic circuit is not satisfiable (Fujita pg. 4 col. 2, implicitly eliminating all detectable faults. Please note after all detectable faults are eliminated, the remaining faults are the ones that were not satisfiable and are undetected).
Sinanoglu, Forte, and Fujita are analogous arts because they are in the same field of endeavor of test patterns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Fujita’s solving a set of SAT problems by implicitly eliminating all detectable faults with the computing device of Sinanoglu-Forte. This modification would have been obvious to one of ordinary skill in the art at the time of filing because it makes the solving process more efficient (Fujita Abstract).
As per claim 9:
Sinanoglu, Forte, and Fujita further teach the computing device of claim 8 wherein to determine the input test pattern associated with the corresponding stuck-at fault comprises to: determine a distinguishing input pattern for the corresponding locked logic circuit in response to a determination that the corresponding locked logic circuit is satisfiable (Fujita Abstract and Fig. 3, in response to a determination of satisfiability, generate test vectors), wherein the input test pattern comprises the distinguishing input pattern (Fujita pg. 4 col. 1, a set of complete test vectors for all combinations of multiple stuck-at faults which are detectable is generated).
As per claim 11:
Sinanoglu and Forte teach the computing device of claim 10.
Sinanoglu and Forte do not explicitly disclose wherein to perform the Boolean satisfiability attack comprises to determine a plurality of distinguishing input patterns for the locked logic circuit, wherein the plurality of distinguishing input patterns comprises the input test pattern associated with each stuck-at fault that is not a redundant fault. However, Fujita discloses wherein to perform the Boolean satisfiability attack comprises to determine a plurality of distinguishing input patterns for the locked logic circuit, wherein the plurality of distinguishing input patterns comprises the input test pattern associated with each stuck-at fault that is not a redundant fault (Fujita Abstract and Fig. 3, in response to a determination of satisfiability, also meaning the stuck-at fault is detectable, generate test vectors. Please note a set of complete test vectors for all combinations of multiple stuck-at faults which are detectable is generated as stated in Fujita pg. 4 col. 1).
Conclusion
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/JEFFREY ANDREW YANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111