DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements (IDS) were filed on 04/22/2024, 11/04/2025, and 01/14/2026 have been acknowledged and considered by examiner.
Response to Arguments
Applicant’s arguments for the rejection of claims under 35 U.S.C. § 103 have been fully considered but are moot because the new ground of rejection does not rely on any reference(s) applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 9 and 11-14, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190206777 A1 (Koller) in view of US 20040110401 A1 (DelPrete).
With regards to claim 1, Koller teaches an offset interposer for electrically coupling a Device Under Test (DUT) to a test circuit board (“a die 102 communicatively coupled to a circuit board 104 of an electronic device with an interposer 106” [0020]),
the interposer comprising: a plurality of upper conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the DUT; a plurality of lower conductive pillars configured to be electrically coupled to a corresponding plurality of contact pads of the test circuit board (“the interposer 106 can communicatively couple the die 102 to the circuit board 104 through the interposer 106 and the plurality of die interconnects 108 and corresponding board interconnects 110” [0020]; ”the die interconnects 108 or the board interconnects 110 can include, but are not limited to, conductive pillars” [0021]),
and wherein a subset of the plurality of upper conductive pillars are offset with respect to a corresponding subset of the plurality of lower conductive pillars (“the die interconnect 108 is disposed at an angle (non-zero angle) with the board interconnect 110 along the normal axis 218” [0024]);
and a substrate (“dielectric layer 212” [0022]; Fig. 2) having a plurality of diagonal vias oriented at an angle to a plane of the substrate (“angled vias 220” [0022]; Fig. 2),
wherein a first diagonal via of the plurality of diagonal vias is angled with respect to a second diagonal via of the plurality of diagonal vias (“the longitudinal axes of the plurality of vias 220 can be disposed at the same or different angles from the normal axis 218” [0025]),
wherein the substrate is located between the plurality of upper conductive pillars and the plurality of lower conductive pillars (“dielectric layer 212 having a first surface 214 and a second surface 216” [0022]),
and wherein each of the plurality of diagonal vias is configured to electrically couple a corresponding one of the subset of the plurality of upper conductive pillars with a corresponding one of the subset of the plurality of lower conductive pillars (“the angled via 220 can electrically couple the die interconnect 108 to the board interconnect 110” [0024]).
Although Koller teaches the conductive pillars, it does not teach that the pillars are compressible.
However, DelPrete teaches compressible conductive pillars (“the conductive elastomeric contacts 44 compress” [0035]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductive pillars of Koller to incorporate the teachings of DelPrete wherein the conductive pillars are compressible to “be resistant to distortion due to applied compressive forces that might adversely affect either the conductivity or positional accuracy of the contacts” [0007].
With regards to claim 2, Koller as modified by DelPrete teaches wherein each of the plurality of diagonal vias is constructed by forming a diagonal through hole and plating the diagonal through hole with a conductive material (“the angled via can be a plated through-hole” and “can be constructed from a conductive material including” Koller [0023])
With regards to claim 3, Koller as modified by DelPrete teaches wherein the diagonal through hole is constructed by diagonal drilling or machining (“the aperture can be formed by mechanical drilling, water drilling, or other aperture forming process” Koller [0039]).
With regards to claim 5, Koller as modified by DelPrete teaches wherein each of the plurality of upper compressible conductive pillars and each of the plurality of lower compressible conductive pillars are cylindrical (“the columnar contacts 44 extending from the substrate 42 may be frustums, generally cylindrical” DelPrete [0032]).
With regards to claim 6, Koller as modified by DelPrete teaches wherein each of the plurality of upper compressible conductive pillars and each of the plurality of lower compressible conductive pillars are tapered (“the columnar contacts 44 extending from the substrate 42 may be frustums, generally cylindrical” DelPrete [0032]).
With regards to claim 7, Koller as modified by DelPrete teaches wherein at least one of an upper surface or a lower surface of the substrate is flat (“normal axis 218 that is perpendicular with the first surface 214, the second surface 216, or both” Koller [0022] and Fig. 2 shows the surfaces to be flat).
With regards to claim 9, Koller as modified by DelPrete teaches wherein each of the plurality of diagonal vias are angled between 15 degrees and 60 degrees with respect to a normal to the substrate (“the angle A can be an angle between 1 and 89 degrees” Koller [0024]).
With regards to claim 11, Koller teaches a method for fabricating an interposer having a substrate with a plurality of diagonal vias for electrically interconnecting a device-under-test (DUT) to a test circuit (“a die 102 communicatively coupled to a circuit board 104 of an electronic device with an interposer 106” [0020]; “interposer including at least one angled via, such as a plurality of angled vias 220” [0022]),
the method comprising: forming a plurality of diagonal through holes in the substrate of the interposer; depositing into the plurality of diagonal through holes a conductive material to form the plurality of diagonal vias (“the angled via can be constructed by forming an aperture between a first surface and a second surface of a dielectric layer” and “the angled via can include a conductive material filling the aperture” [0031])
oriented at an angle to a plane of the substrate (“angled vias 220” [0022]; Fig. 2), wherein a first diagonal via of the plurality of diagonal vias is angled with respect to a second diagonal via of the plurality of diagonal vias (“the longitudinal axes of the plurality of vias 220 can be disposed at the same or different angles from the normal axis 218” [0025]);
and electrically coupling the plurality of diagonal vias to a corresponding plurality of upper pillars and a corresponding plurality of lower pillars (“the angled via 220 can electrically couple the die interconnect 108 to the board interconnect 110” [0024]),
wherein the plurality of upper pillars are located at an upper surface of the substrate, and wherein the plurality of lower pillars are located at a lower surface of the substrate (first interconnect 108 and second interconnect 110; Fig. 1),
and wherein the plurality of upper pillars and the plurality of lower pillars are configured to provide corresponding interconnections between the DUT and the test circuit, respectively (“the die 102 can be electrically coupled to the interposer 106 with a plurality of interconnects 108. The interposer 106 can be electrically coupled to the circuit board 104 through a plurality of interconnects 110” [0020]).
Although Koller teaches that the interconnects can include pillars (”the die interconnects 108 or the board interconnects 110 can include, but are not limited to, conductive pillars” [0021]), it does not teach that the pillars are elastomeric.
However, DelPrete teaches elastomeric conductive pillars (“the conductive elastomeric contacts 44 compress” [0035])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductive pillars of Koller to incorporate the teachings of DelPrete wherein the conductive pillars are compressible to “be resistant to distortion due to applied compressive forces that might adversely affect either the conductivity or positional accuracy of the contacts” [0007].
With regards to claim 12, Koller as modified by DelPrete teaches wherein the diagonal through holes are formed by one or more of drilling, ultrasonic machining or laser machining (“the aperture can be formed by mechanical drilling, water drilling, or other aperture forming process” Koller [0039]).
With regards to claim13, Koller as modified by DelPrete teaches wherein the conductive material is metallic (“The angled via 220 can be constructed from a conductive material including, but not limited to, copper, tin, silver, gold,…” Koller [0023]).
With regards to claim 14, Koller as modified by DelPrete teaches wherein the conductive material is embedded in a binder (“The conductive material can be disposed within the aperture by a process including, but not limited to, electroless deposition, vacuum assisted deposition (of, e.g., printed filler material) Koller [0043]).
With regards to claim 16, Koller as modified by DelPrete teaches wherein each of the plurality of upper elastomeric pillars and each of the plurality of lower elastomeric pillars are cylindrical (“the columnar contacts 44 extending from the substrate 42 may be frustums, generally cylindrical” DelPrete [0032]).
With regards to claim 17, Koller as modified by DelPrete teaches wherein each of the plurality of upper elastomeric pillars and each of the plurality of lower elastomeric pillars are tapered (“the columnar contacts 44 extending from the substrate 42 may be frustums, generally cylindrical” DelPrete [0032]).
With regards to claim 19, Koller as modified by DelPrete teaches wherein each of the plurality of diagonal vias are angled between 15 degrees and 60 degrees with respect to a normal to the substrate (“the angle A can be an angle between 1 and 89 degrees” Koller [0024]).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190206777 A1 (Koller) in view of US 20040110401 A1 (DelPrete) and US 20040178812 A1 (Karavakis).
With regards to claim 4, Koller as modified by DelPrete does not teach explicitly teach wherein the plated diagonal through hole is reinforced by an epoxy.
However, Karavakis teaches wherein the plated diagonal through hole is reinforced by an epoxy (“vias… are filled with paste… Paste may be any one of a number of conductive pastes… such as, for example, and without limitation, a Ag conductive paste, a Au conductive paste, a Cu conductive paste…” [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the diagonal vias of Koller as modified by DelPrete to incorporate the teachings of Karavakis wherein the plated diagonal through hole is reinforced by an epoxy to be able to take up vertical movements or movements in a Z-direction caused during testing by non-planarity of contactors on the substrate [0030].
With regards to claim 15, Koller as modified by DelPrete does not explicitly teach wherein the binder is an epoxy material.
However, Karavakis teaches wherein the plated diagonal through hole is reinforced by an epoxy (“vias… are filled with paste… Paste may be any one of a number of conductive pastes… such as, for example, and without limitation, a Ag conductive paste, a Au conductive paste, a Cu conductive paste…” [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the diagonal vias of Koller as modified by DelPrete to incorporate the teachings of Karavakis wherein the plated diagonal through hole is reinforced by an epoxy to be able to take up vertical movements or movements in a Z-direction caused during testing by non-planarity of contactors on the substrate [0030].
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190206777 A1 (Koller) in view of US 20040110401 A1 (DelPrete) and US 20200006286 A1 (Chen).
With regards to claims 8 and 18, Koller as modified by DelPrete does not teach wherein at least one of an upper surface or the lower surface of the substrate is curved to accommodate a corresponding curved surface of the DUT.
However, Chen teaches wherein at least one of an upper surface or the lower surface of the substrate is curved to accommodate a corresponding curved surface of the DUT (“the circuit substrate is bowed, arched or curved with one or more curvatures corresponding to the warpage of the package structure” [0012]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the interposer of Koller as modified by DelPrete to incorporate the teachings of Chen wherein at least one of an upper surface or the lower surface of the substrate is curved to accommodate a corresponding curved surface of the DUT to reduce the impact caused by warpage from the coefficient of thermal expansion (CTE) mismatch [0012].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20240027522 A1 (Tanaka)
US 20120038046 A1 (Lin)
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/OSAMAH MURSHED/Examiner, Art Unit 2858
/JENNIFER BAHLS/Primary Examiner, Art Unit 2853
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