Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/22/2024 was filed before the mailing date of the Non-final rejection on 6/24/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 4/22/2024 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ ARRANGEMANT OF A PLURALITY OF POWER CHIPS MOUNTED ON A SUBSTRATE IN A POWER MODULE ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 12, 13, and 15-17 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Bayerer et al. (US 2016/0056132).
With respect to Claim 1, Bayerer a substrate 9 comprising a dielectric insulation layer 70 and a first metallization layer 71-73 arranged on a surface of the dielectric insulation layer. The first metallization layer 71-73 comprises a first
section, a second section, and a third section. A first semiconductor body 1 and an identical second semiconductor body 1 (i.e. adjacent semiconductor body) arranged on the first metallization layer 71. Each of the first semiconductor body 1 and the second semiconductor body 1 has a first contact pad (i.e. located under first connection location 41), a second contact pad (i.e. located under first connection location 41), and a third contact pad 13 arranged on a top side of the respective semiconductor body 1 that faces away from the substrate 9. The third contact pad 13 of the first semiconductor body 1 is electrically coupled to the third section 73 of the first metallization layer by means of a first electrical connection element 5. The third contact pad 13 of the second semiconductor body 1 is electrically coupled to the third section 73 of the first metallization layer by means of a second electrical connection element 5.
The semiconductor module arrangement further comprises at least one third
terminal element 6 arranged on the third section 73. A first current path between the third contact pad 13 of the first semiconductor body and the at least one third terminal element 6 provides identical voltage and current transfer characteristics as a
second current path (i.e. since both first and second semiconductor bodies are electrically connected to the same side of the third section which is directly connected third terminal element) between the third contact pad of the second semiconductor body (202) and the at least one third terminal element. Each of the first electrical connection element and the second electrical connection elements 5 comprises at least one of one or more bonding wires, one or more bonding ribbons, a connection rail, or a
section of an additional metallization layer of the substrate (10) that is
contacted by one or more corresponding vias (see paragraphs 41-55; Figs. 1-6).
With respect to Claim 2, Bayerer teaches the first current path and the second current path exhibit at least one of identical ohmic behaviors, identical inductive behaviors, and or identical capacitive behaviors since the wire lengths and semiconductor bodies MOSFET are identical (see paragraph 43); Fig. 1) .
With respect to Claim 3, Bayerer teaches the first current path is formed by the first electrical connection element 5 and a first segment of the third section 71 arranged between a first connection point and the at least one third terminal element 6. The first connection point is a point at which the first electrical connection element 5 is connected to the third section 71. The second current path is formed by the second electrical connection element 5 and a second segment of the third section 71 arranged between a second connection point and the at least one third terminal element. The second connection point is a point at which the second electrical connection element is connected to the third section (see Figs. 1-6).
With respect to Claim 4, Bayerer teaches the first contact pad (i.e. located under first connection location 41) of the first semiconductor body 1 and the first
contact pad (i.e. located under first connection location 41) of the second semiconductor body (202) are electrically coupled to the first section of the first metallization layer 71. The second contact pad of the first semiconductor body and the second
contact pad of the second semiconductor body 1 are electrically
coupled to the second section of the first metallization layer 71 (see Figs. 1-6).
With respect to Claim 5, Bayerer teaches the third section 71 is arranged horizontally between the first semiconductor body 1 and the second semiconductor body 1 (see Figs. 1-6).
With respect to Claim 6, Bayerer teaches the first semiconductor body 1 is arranged point symmetrical to the second semiconductor body 1 about a center of symmetry (see Figs. 1-6).
With respect to Claim 8, Bayerer teaches the first semiconductor body 1 and the second semiconductor body 1 are arranged on the same side with respect to the third section 71 in a second horizontal direction (see Figs. 1-6).
With respect to Claim 9, Bayerer teaches an orientation of the first semiconductor body 1 corresponds to an orientation of the second semiconductor body 1 (see Figs. 1-6).
With respect to Claim 9, Bayerer teaches the third section 71 of the first metallization layer and the at least one third terminal element 6 arranged thereon are arranged distant from the first semiconductor body 1 and the second semiconductor body 1 in the second horizontal direction (see Figs. 1-6).
With respect to Claim 12, Bayerer teaches the first semiconductor body 1 and the second semiconductor body 1 are arranged on the second section 72 of the first metallization layer (see Figs. 1-6).
With respect to Claim 13, Bayerer teaches each of the first contact pad of the first semiconductor body 1 and the first contact pad of the second semiconductor body 1 is electrically coupled to the first section 71 of the first metallization layer by means of an electrical connection element. Each of the second contact pad of the first semiconductor body 1 and the second contact pad of the second semiconductor body 2 are electrically coupled to the second section 72 of the first metallization layer
by means of an electrical connection element. Each of the electrical connection elements 5 comprises at least one of one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate that is contacted by one or more corresponding vias (see Figs. 1-6).
With respect to Claim 15, Bayerer teaches one or more second terminal elements 4 (i.e. bonding wire) on the second section of the first metallization layer. The third section, in the second horizontal direction, is arranged between the
one or more second terminal elements and the first and second semiconductor
bodies 1 (see Figs. 1-6).
With respect to Claim 16, Bayerer teaches a fourth section of the first metallization layer. A third semiconductor body 1 and an identical fourth semiconductor body 1 (i.e. the top pair of semiconductor body 1) arranged on the first metallization layer 71. Each of the third semiconductor body and the fourth semiconductor body has a first contact pad, a second contact pad, and a third contact pad 13 arranged on a top side of the respective semiconductor body 1. The top side is a side that faces away from the substrate 9, wherein an orientation of the third semiconductor body 1 and the fourth semiconductor body 1 corresponds to an orientation of the first and the second
semiconductor body the third semiconductor body and the fourth semiconductor body are arranged on the same side with respect to the third section and the
fourth section as the first semiconductor body and the second semiconductor body. The third contact pad 13 of the third semiconductor body 1 is electrically coupled
to the fourth section of the first metallization layer by means of a third electrical connection element. The third contact pad of the fourth semiconductor body 1 is electrically coupled to the fourth section of the first metallization layer by means of
a fourth electrical connection element. The semiconductor module arrangement further comprises at least one fourth terminal element 6 arranged on the fourth section . A third current path between the third contact pad of the third semiconductor body 1 and the at least one fourth terminal element provides identical voltage and current transfer characteristics as a fourth current path between the third contact pad of the fourth semiconductor body and the at least one fourth terminal element. Each of the third electrical connection element and the fourth electrical connection element comprises at least one of one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate 9 that is
contacted by one or more corresponding vias (see paragraphs 41-55; Figs. 1-6).
With respect to Claim 17, Bayerer teaches the first contact pad of the third semiconductor body and the first contact pad (i.e. attached to bonding wire 4) of the fourth semiconductor body are electrically coupled to the first section of the first metallization layer. The second contact pad of the third semiconductor body and the second contact pad of the fourth semiconductor body are electrically coupled to the second section of the first metallization layer (see Figs. 1-6).
Allowable Subject Matter
8. Claim 20 is allowed.
9. Claims 7, 11, 14, 18, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record teaches or suggest the combination of
one third terminal element arranged at the center of symmetry. The one or more dimensions and the one or more materials of the first electrical connection element are identical to the one or more dimensions and the one or more materials of the second electrical connection element. A length of the first segment of the third section
is identical to a length of the second segment of the third section in claim 7.
The third section has a length in a first horizontal direction -perpendicular to the second horizontal direction. The length of the third section is equal to or greater than the sum of a length of the first semiconductor body, a length of the second
semiconductor body. A distance between the first semiconductor body
and the second semiconductor body in the first horizontal direction in claim 11.
The second section of the first metallization layer horizontally surrounds the third section in claim 14.
The second section of the first metallization layer horizontally surrounds the fourth section in claim 18.
A fifth section of the first metallization layer, wherein the second section of the first metallization layer horizontally surrounds the fifth section, the third section, in the second horizontal direction, is arranged between the fifth section. The first semiconductor body and the second semiconductor body. The fourth section in the second horizontal direction, is arranged between the fifth section and the third semiconductor body and the fourth semiconductor body in claim 19.
The second section horizontally surrounds each of the third section
the fourth section, and the fifth section.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention. At least one fifth terminal element arranged on the fifth section of the first metallization layer in claim 20.
Conclusion
10. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/June 24, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
Prosecution Insights