DETAILED ACTION
This Non-Final Action is responsive to communications: RCE filed 07/01/2026.
Applicant amended claim 13, cancelled claims 9-12; applicant added new claims 21-24. Claims 1-8, and 13-24 are pending. Claims 1, 14, and 21 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/01/2026 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic priority details.
No Information Disclosure Statement
5. No IDS has been filed as of this office action date.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 21, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2023/0185460 A1).
Regarding independent claim 21, Kim teaches a method (para [0029], Fig. 21 method: “… FIG. 21 illustrates an example of the command protocol of the memory system when the memory system updates the count data based on the precharge command…”) comprising:
transmitting, by a memory controller (Fig. 1: 30, 210 combined) and to a memory device (Fig. 1: 200),
an activate command (Fig. 21: ACT1) that causes the memory device to read an activation count that is stored in a subset of memory cells of the memory device (in context of para [0210]: “count data stored in a target memory cell” is accessed, read when ACT1 is issued to be used in subsequent operations); and
transmitting, by the memory controller and to the memory device, a precharge command (Fig. 21: PRE) that causes the memory device to write an updated activation count to the subset of the memory cells prior to executing the precharge command (para [0210]: “…precharge command PRE including a flag designating an internal read-update-write operation on the count data stored in a target memory cell designated by a target row address…”),
the activate command (Fig. 21: ACT1) and the precharge command (Fig. 21: PRE) separated in time by a timing offset (See Fig. 21).
Regarding claim 23, Kim teaches the method of claim 21, wherein: the activate command is associated with a row of the memory device (para [0209]: target row address); and
the precharge command causes the memory device to write the updated activation count to the subset of the memory cells corresponding to the row (para [0209]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
12. Claims 1, 4, 6-8, 14-16, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over Zheng et al. (US 9,104,646 B2), in view of Kim (US 2023/0185460 A1).
Regarding independent claim 1, Zheng teaches an apparatus (Fig. 1: 10 memory system) comprising:
a memory device (Fig. 1: 40 memory device) comprising:
at least one bank comprising memory cells (Fig. 1: array and associated peripheral circuitry),
wherein a subset of the memory cells (Fig. 1: combined row with 52, 54 cells) is configured to store data associated with usage-based disturbance (col. 5, Lines 4-22: “…disturbance warning circuits 54 are resistive memory cells that have a programmable resistance…sufficient change in the resistance of the disturbance warning circuit 54 occurs, the threshold is crossed and the disturbance control circuit 54 determines that a disturbance condition sufficient to trigger correction…”); and
circuitry (Fig. 1: 56 “disturbance control circuit” with “disturbance recovery logic”) configured to mitigate usage-based disturbance within the bank based on the data (col. 5, lines 50-62; col. 6, lines 1-9: “disturbance recovery” operation),
the memory device (Fig. 1: 40) configured to:
receive, from a memory controller (Fig. 1: “memory controller 20”, see col. 9, lines 66-67; col. 10, lines 3-6), two commands that are separated in time by a timing offset (Fig. 7: ACT at timing A, PRE at timing C);
generate an internal read command (Fig. 7: internal command associated with operation “disturbance detected” at timing B) based on a first command (Fig. 7: ACT at timing A. see also col. 9, lines 66-67) of the two commands to cause the memory device to read the data from the subset of the memory cells (col. 5, lines 59-67: “…disturbance control circuit 56 accesses the disturbance warning circuits 54 to determine whether the state of one or more of the disturbance warning circuits 54 indicates the presence of an actionable disturbance condition…”); and
generate an internal write command (Fig. 7: internal command associated with operation “disturbance recovery” at timing C) based on a second command (Fig. 7: PRE. See also col. 10, lines 7-9) of the two commands
to cause the memory device to write modified data (data used for reset and/ or reprogramming) generated by the circuitry to the subset of the memory cells (in context of col. 6, lines 7-9, lines 25-32: “reset” is applied on disturbance warning circuit cells and “reprogramming” is done on active row of cells).
Zheng is silent with respect to “…receive, from a memory controller, two commands that are separated intime by a timing offset, the two commands comprising a first command and a second command, the first command comprising an activate command, the second command comprising a precharge command; generate, responsive to reception of the first command, an internal read command that causes the memory device to read the data from the subset of the memory cells; and generate, responsive to reception of the second command, an internal write command that causes the memory device to write modified data generated by the circuitry to the subset of the memory cells…”
Kim teaches
receive, from a memory controller, two commands that are separated in time by a timing offset, the two commands comprising a first command and a second command (See Fig. 21: ACT1 and PRE commands separated in timing),
the first command comprising an activate command (Fig. 21: ACT1), the second command comprising a precharge command (Fig. 21: PRE);
generate, responsive to reception of the first command, an internal read command that causes the memory device to read the data from the subset of the memory cells (Fig. 21 in context of para [0209]: “count data stored in a target memory cell” is accessed, read when ACT1 is issued); and
generate, responsive to reception of the second command, an internal write command that causes the memory device to write modified data generated by the circuitry to the subset of the memory cells (Fig. 21 in context of para [0209]: “…precharge command PRE including a flag designating an internal read-update-write operation on the count data stored in a target memory cell designated by a target row address…”).
Both Zheng and Kim are in the same field of endeavor of hammer refresh operation improvement of DRAM and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date to combine the teachings of Kim into the teachings of Zhang such that ACT and PRE command architecture and timing can be employed for efficient, reliable control of row hammer refresh operation “…manage row hammer of all of a plurality of memory cell rows while maintaining performance…” (Kim para [0005]).
Regarding claim 4, Zheng and Kim teach the apparatus of claim 1. Zheng teaches wherein the memory device is configured to read the data from the subset of the memory cells based on the internal read command prior to receiving the second command (Fig. 7 in context of col. 9, lines 63-67; col. 10, lines 1-13).
Regarding claim 6, Zheng and Kim teach the apparatus of claim 1. Zheng teaches wherein the memory device is configured to write the modified data to the subset of the memory cells prior to receiving a subsequent command (see Fig. 7: disturbance recovery is completed before subsequent ACT command).
Regarding claim 7, Zheng and Kim teach the apparatus of claim 6. Zheng teaches wherein a timing offset between the second command and a subsequent command corresponds to a precharge time (tRP) (see Fig. 7: tRP).
Regarding claim 8, Zheng and Kim teach the apparatus of claim 1. Zheng teaches wherein the subset represents (subset is inclusive of) a subset of the memory cells within each row of the bank (Fig. 1: 54 in row associated with 52, 54. See context of col. 4, lines 61-63).
Regarding independent claim 14, Zheng teaches a method comprising: receiving, by a memory device (Zheng teaches an apparatus (Fig. 1: 10 memory system) comprising: a memory device (Fig. 1: 40 memory device) comprising: at least one bank comprising memory cells (Fig. 1: array and associated peripheral circuitry), wherein a subset of the memory cells (Fig. 1: combined row with 52, 54 cells) is configured to store data associated with usage-based disturbance (col. 5, Lines 4-22: “…disturbance warning circuits 54 are resistive memory cells that have a programmable resistance…sufficient change in the resistance of the disturbance warning circuit 54 occurs, the threshold is crossed and the disturbance control circuit 54 determines that a disturbance condition sufficient to trigger correction…”); and circuitry (Fig. 1: 56 “disturbance control circuit” with “disturbance recovery logic”) configured to mitigate usage-based disturbance within the bank based on the data (col. 5, lines 50-62; col. 6, lines 1-9: “disturbance recovery” operation),
a first command from a memory controller; executing, by the memory device, an internal read command associated with usage-based disturbance mitigation based on the first command; receiving, by the memory device, a second command from the memory controller; and executing, by the memory device, an internal write command associated with usage-based disturbance mitigation based on the second command (Zheng teaches the memory device (Fig. 1: 40) configured to: receive, from a memory controller (Fig. 1: “memory controller 20”, see col. 9, lines 66-67; col. 10, lines 3-6), two commands that are separated in time by a timing offset (Fig. 7: ACT at timing A, PRE at timing C); generate an internal read command (Fig. 7: internal command associated with operation “disturbance detected” at timing B) based on a first command (Fig. 7: ACT at timing A. see also col. 9, lines 66-67) of the two commands to cause the memory device to read the data from the subset of the memory cells (col. 5, lines 59-67: “…disturbance control circuit 56 accesses the disturbance warning circuits 54 to determine whether the state of one or more of the disturbance warning circuits 54 indicates the presence of an actionable disturbance condition…”); and generate an internal write command (Fig. 7: internal command associated with operation “disturbance recovery” at timing C) based on a second command (Fig. 7: PRE. See also col. 10, lines 7-9) of the two commands to cause the memory device to write modified data (data used for reset and/ or reprogramming) generated by the circuitry to the subset of the memory cells (in context of col. 6, lines 7-9, lines 25-32: “reset” is applied on disturbance warning circuit cells and “reprogramming” is done on active row of cells))
Zheng is silent with respect to: responsive to the receiving of the first command, an internal read command that causes the memory device to read an activation count associated with usage-based disturbance mitigation from a subset of memory cells within a row and responsive to the receiving of the second command, an internal write command that causes the memory device to write an updated activation count to the subset of memory cells within the row.
Kim teaches -
executing, by the memory device and responsive to the receiving of the first command (Fig. 21: ACT1), an internal read command that causes the memory device to read an activation count associated with usage-based disturbance mitigation from a subset of memory cells within a row (Fig. 21 in context of para [0209]: “count data stored in a target memory cell” is accessed, read when ACT1 is issued);
receiving, by the memory device, a second command (Fig. 21: PRE) from the memory controller that is different from the first command (See Fig. 21); and
executing, by the memory device and responsive to the receiving of the second command, an internal write command that causes the memory device to write an updated activation count to the subset of memory cells within the row (Fig. 21 in context of para [0209]: “…precharge command PRE including a flag designating an internal read-update-write operation on the count data stored in a target memory cell designated by a target row address…”).
Both Zheng and Kim are in the same field of endeavor of hammer refresh operation improvement of DRAM and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date to combine the teachings of Kim into the teachings of Zhang such that ACT and PRE command architecture and timing can be employed for efficient, reliable control of row hammer refresh operation “…manage row hammer of all of a plurality of memory cell rows while maintaining performance…” (Kim para [0005]).
Regarding claim 15, Zheng and Kim teach the method of claim 14. Kim teaches wherein the receiving of the first command comprises receiving an activate command from the memory controller (Fig. 21: ACT1, para [0209]).
Regarding claim 16, Zheng and Kim teach the method of claim 14. Kim teaches wherein the receiving of the second command comprises receiving a precharge command from the memory controller. (Fig. 21: PRE, para [0209]).
Regarding claim 20, Zheng and Kim teach the method of claim 14. Zheng teaches wherein the executing of the internal read command comprises reading, by the memory device and based on the internal read command, data associated with usage-based disturbance prior to receiving the second command. (See claim 1 and claim 4 rejection analysis. See also Fig. 7 disclosure)
Allowable Subject Matter
Claims 2-3, 5, 13, 17-19, 22, and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Response to Arguments
Based on updated search, Kim reference was found and previously indicated allowable subject matters are being withdrawn.
Applicant’s arguments with respect to independent claim(s) and new claims have been considered but are moot because new grounds of rejection added based on newly added reference. The new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In general, applicant's arguments filed 07/01/2026 regarding claims have been fully considered but they are not persuasive because applicant has not provided sufficient reasons.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Kwon (US 2011/0122687 A1): Fig. 1-Fig. 4 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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