DETAILED ACTION
This Final Action is responsive to communications: 02/18/2026.
Applicant amended claims 1-3, 5, 9-10, and 14. Applicant did not cancel any claims. Applicant did not add any new claims. Additional drawing, spec amendments, and all claim amendments submitted are accepted and being entered. Claims 1-20 are pending. Claims 1, 9, and 14 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic priority details.
No Information Disclosure Statement
5. No IDS has been filed as of this office action date.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 9-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zheng et al. (US 9,104,646 B2).
Regarding independent claim 9, Zheng teaches an apparatus (Fig. 1: 10 memory system) comprising:
a memory device (Fig. 1: 40 memory device) comprising a plurality of memory cells arranged in rows (Fig. 1: combined row with 52, 54 cells),
a subset of the memory cells (Fig. 1: 54 cells in row) configured to store data associated with usage-based disturbance in the rows (col. 5, Lines 4-22: “…disturbance warning circuits 54 are resistive memory cells that have a programmable resistance…sufficient change in the resistance of the disturbance warning circuit 54 occurs, the threshold is crossed and the disturbance control circuit 54 determines that a disturbance condition sufficient to trigger correction…”),
the memory device (Fig. 1: 40) configured to:
receive, from a memory controller (Fig. 1: “memory controller 20”, see col. 9, lines 66-67; col. 10, lines 3-6), an activate command (Fig. 7: ACT at timing A); and
read (detection of disturbance cells “detected” requires sensing/ reading), responsive to reception of the activate command (see Fig. 7: ACT command and associated delay), the data from the subset of the memory cells (Fig. 7: “disturbance detected” is performed at timing B which requires sensing states of 54 cells. See also Fig. 2-FGIg. 3. Col. 7, lines 34-42).
Regarding claim 10, Zheng teaches the apparatus of claim 9, wherein the memory device is configured to: receive, from the memory controller (Fig. 1: “memory controller 20”, see col. 9, lines 66-67; col. 10, lines 3-6), a precharge command that is separated in time from the activate command (Fig. 7: PRE at timing C); and
Write, responsive to reception of the precharge command (Fig. 7: PRE at timing C), modified data generated (data used for reset and reprogramming during recovery) based on the data to the subset of the memory cells based on the precharge command (Fig. 7: disturbance recovery after PRE. See in context of col. 6, lines 7-9, lines 25-32: “reset” is applied on disturbance warning circuit cells and “reprogramming” is done on active row of cells).
Regarding claim 11, Zheng teaches the apparatus of claim 10, wherein the memory device is configured to read the data from the subset of the memory cells prior to receiving the precharge command (Fig. 7 in context of col. 9, lines 63-67; col. 10, lines 1-13: during disturbance detection, states of 54 cells are sensed).
Regarding claim 12, Zheng teaches the apparatus of claim 10, wherein the memory device is configured to write the modified data to the subset of the memory cells prior to receiving a subsequent command (see Fig. 7: disturbance recovery is completed before subsequent ACT command).
Regarding claim 13, Zheng teaches the apparatus of claim 9, wherein: each row includes the subset of the memory cells configured to store the data associated with usage-based disturbance (Fig. 1: 54 in row associated with 52, 54. See context of col. 4, lines 61-63);
the activate command is associated with a particular row (col. 7, lines 25-30); and
the memory device is configured to read the data from the row associated with the activate command (col. 9, lines 66-67: disturbance detect).
Allowable Subject Matter
Claims 1-8, and 14-20 are indicated as allowable.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Response to Arguments
Applicant's arguments filed 02/18/2026 regarding claims 9-13 have been fully considered but they are not persuasive because applicant has not provided sufficient reasons. (See Remarks pages 14-15)
Regarding claims 9-13, applicant should submit an argument under the heading “Remarks” pointing out disagreements with the examiner’s contentions. Applicant must also discuss the references applied against the claims, explaining how the claims avoid the references or distinguish from them. See new formulated rejection. Current Claim 9 rejection is supported by previously communicated rejections of claim 1. Zheng teaches an apparatus (Fig. 1: 10 memory system) comprising: a memory device (Fig. 1: 40 memory device) comprising: at least one bank comprising memory cells (Fig. 1: array and associated peripheral circuitry), wherein a subset of the memory cells (Fig. 1: combined row with 52, 54 cells) is configured to store data associated with usage-based disturbance (col. 5, Lines 4-22: “…disturbance warning circuits 54 are resistive memory cells that have a programmable resistance…sufficient change in the resistance of the disturbance warning circuit 54 occurs, the threshold is crossed and the disturbance control circuit 54 determines that a disturbance condition sufficient to trigger correction…”); and circuitry (Fig. 1: 56 “disturbance control circuit” with “disturbance recovery logic”) configured to mitigate usage-based disturbance within the bank based on the data (col. 5, lines 50-62; col. 6, lines 1-9: “disturbance recovery” operation), the memory device (Fig. 1: 40) configured to: receive, from a memory controller (Fig. 1: “memory controller 20”, see col. 9, lines 66-67; col. 10, lines 3-6), two commands that are separated in time by a timing offset (Fig. 7: ACT at timing A, PRE at timing C); generate an internal read command (Fig. 7: internal command associated with operation “disturbance detected” at timing B) based on a first command (Fig. 7: ACT at timing A. see also col. 9, lines 66-67) of the two commands to cause the memory device to read the data from the subset of the memory cells (col. 5, lines 59-67: “…disturbance control circuit 56 accesses the disturbance warning circuits 54 to determine whether the state of one or more of the disturbance warning circuits 54 indicates the presence of an actionable disturbance condition…”); and generate an internal write command (Fig. 7: internal command associated with operation “disturbance recovery” at timing C) based on a second command (Fig. 7: PRE. See also col. 10, lines 7-9) of the two commands to cause the memory device to write modified data (data used for reset and/ or reprogramming) generated by the circuitry to the subset of the memory cells (in context of col. 6, lines 7-9, lines 25-32: “reset” is applied on disturbance warning circuit cells and “reprogramming” is done on active row of cells).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Kwon (US 2011/0122687 A1): Fig. 1-Fig. 4 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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