DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, claims 1-2, 5-8, 11-12 and 15, in the reply filed on 07/21/2026 is acknowledged.
IDS
The IDS document(s) filed on 04/22/2024 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 8, the recitation of “locally provided” (emphasis added) is unclear.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-8, 11-12, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kaya et al. (JP 6414861 B2, translation provided), hereafter “Kaya”.
As to claim 1, Kaya teaches a semiconductor device comprising:
a base body (BSE, Fig. 4, Page 4, Par. 4) of a first conductivity-type (p-type);
a first well region (BDF, Page 4, Par. 4) of a second conductivity-type (n-type) provided in the base body and including a high-side circuit;
a first voltage blocking region (LDF+LDR, Page 4, Par. 8 and Page 5, Par. 4) of the second conductivity-type (n-type)having a lower impurity concentration (n-) than the first well region and provided along a circumference of the first well region;
a second voltage blocking region (left IDF of Fig. 4, Page 4, Par. 2) of the first conductivity-type (p-type) provided in contact with the first voltage blocking region on an outer circumferential side of the first voltage blocking region;
a first level shift element (LSC, Fig. 2: SO, GE, DR, Fig. 3, Page 2, Par. 6) provided to encompass a part of the first voltage blocking region (LDR);
a first isolation region (IDF,) of the first conductivity-type (p-type) provided to surround a circumference of the first level shift element; and
a field plate (FP1+FP2, Fig. 32, Page 3, Par. 7 and Page 10, Par. 2) provided over the first voltage blocking region (LDF+LDR) and the first isolation region (IDF) with an insulating film interposed (INSL1, Page 10, Par. 2), the field plate having a first distance (IDF to FP2) from the first isolation region greater than a second distance from the first voltage blocking region (LDF+LDR to FP2).
Kaya fails to disclose the first and second voltage blocking region provided into a circular state, on the other hand Examiner notes Applicant has not specified a criticality to the shape.
It would have been obvious to one of ordinary skill in the art before the effective filing date to obtain the circular state as shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As to claim 2, Kaya teaches the semiconductor device of claim 1, wherein the field plate is elongated across an upper side of the first level shift element with the second distance (Fig. 26 shows FP1 elongated across the upper side of LSC) .
As to claim 5, Kaya teaches the semiconductor device of claim 1, wherein the field plate incudes: a first layer (FP1) provided over the first voltage blocking region (Fig. 33 shows FP1 provided over IDF) while being divided over the first isolation region (Fig. 26 shows FP1 divided over the first isolation region in the vertical direction); and a second layer (FP2) provided over the first isolation region (Fig. 33 shows FP2 provided over IDF).
As to claim 6, Kaya teaches the semiconductor device of claim 5, wherein the first layer is electrically connected to the second layer (FP1 and FP2 are both connected to the drain electrode DRE1, Page 4, Par. 1 and Page 10 Par. 5).
As to claim 7, Kaya teaches the semiconductor device of claim 5, wherein the first layer (FP1) includes polysilicon (Page 4, Par. 9), and the second layer (FP2) includes metal (Page 6, Par. 6 and Page 10, Par. 4).
As to claim 8, Kaya teaches the semiconductor device of claim 5, wherein the second layer is locally provided over the first isolation region (Fig. 33 shows FP2 provided over IDF, see 112b).
As to claim 11, Kaya teaches the semiconductor device of claim 1, wherein the field plate has a spiral-shaped planar pattern (spiral pattern shown in Fig. 25).
As to claim 12, Kaya teaches the semiconductor device of claim 11, wherein: one end of the spiral-shaped planar pattern on an inner circumferential side is connected to a first potential; and another end of the spiral-shaped planar pattern on an outer circumferential side is connected to a second potential lower than the first potential (Page 6, Par. 2).
As to claim 15, Kaya teaches the semiconductor device of claim 1, wherein the first isolation region has a U-shaped planar pattern having two straight parts with ends connected to the second voltage blocking region (see annotated Fig. 3 below).
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Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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