DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election of Claims 1-17, drawn to a device, has been acknowledged. Claims 1-17 and 21-23 remain pending. Claims 18-20 were cancelled.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 10-11, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liebmann et al (TW 202121652).
Regarding Claim 1, Liebmann et al discloses a semiconductor device (2D semiconductor device 299 and 3D semiconductor device 399 [page 7, lines 1-23] Fig 2A-D and Fig 3A-L), comprising:
a first semiconductor layer (region 232 [page 7, lines 24 -35] Fig 2A) and a second semiconductor layer (region 231 [page 7, lines 24-35] Fig 2A) stacked vertically over a substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B), each of the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A) extending laterally across the substrate (301 (not shown in Fig 2A-D) Fig 3A-B); and
a first gate structure (conductive structure 211 [page 7, lines 36-46] Fig 2A) and a second gate structure (conductive structure 212 [page 7, lines 36-46] Fig 2A) extending vertically from the substrate (301 (not shown in Fig 2A-D) Fig 3A-B) and perpendicular to the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A),
the first gate structure (211 Fig 2A) engaging the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A) to form a first transistor (N1 [page 7, lines 12-19] Fig 2A) and a second transistor (P1 [page 7, lines 12-19] Fig 2A), respectively, and
the second gate structure (212 Fig 2A) engaging the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A) to form a third transistor (N2 [page 7, lines 12-19] Fig 2A) and a fourth transistor (P2 [page 7, lines 12-19] Fig 2A), respectively,
wherein: the first gate structure (211 Fig 2A) is laterally adjacent to the second gate structure (212 Fig 2A),
the third transistor (N2 Fig 2A) is an inactive transistor (P1 and N1 function as an open switch, P2 and N2 function as a closing switch [page 7, lines 1-7] Fig 2A, the examiner notes that inactive transistors of CFET are the transistors that are in the off state, which would be N1 and N2), and the second transistor (P1 Fig 2A) and the fourth transistor (P2 Fig 2A) are active transistors (active channel space dh1 and dh2 [page 8, lines 30-50] Fig 2A).
Regarding Claim 3, Liebmann et al discloses the limitations of claim 1 as explained above. Liebmann et al further discloses
wherein: the third transistor (N2 Fig 2A) is coupled to a first source contact (T7 [page 7, lines 20-35] Fig 2A), a first drain contact (T8 [page 7, lines 20-35] Fig 2A), and a first gate contact (gate electrode G4 [page 7, lines 20-35] Fig 2A),
the fourth transistor (P2 Fig 2A) is coupled to a second gate contact (gate electrode G3 [page 7, lines 20-35] Fig 2A),
the first source contact (T7 Fig 2A) and the first drain contact (T8 Fig 2A) are both coupled to a first signal line (shown in annotated Fig 1B), and
the first gate contact (G4 Fig 2A) and the second gate contact (G3 Fig 2A) are both coupled to a second signal line (shown in annotated Fig 1B).
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Regarding Claim 4, Liebmann et al discloses the limitations of claim 1 as explained above. Liebmann et al further discloses
wherein: the third transistor (N2 Fig 2A) is coupled to a first source contact (T7 [page 7, lines 20-35] Fig 2A), a first drain contact (T8 [page 7, lines 20-35] Fig 2A), and a first gate contact (gate electrode G4 [page 7, lines 20-35] Fig 2A),
the fourth transistor (P2 Fig 2A) is coupled to a second gate contact (gate electrode G3 [page 7, lines 20-35] Fig 2A),
one of the first source contact (T7 Fig 2A) and the first drain contact (T8 Fig 2A) is floating (shown to be not directly connected to a ground in Fig 1A/semiconductor device 399 may including floating gate transistors [page 9, lines 23-32] Fig3A), and the first gate contact (G4 Fig 2A) and the second gate contact (G3 Fig 2A) are both coupled to a same signal line (it can be observed in annotated Fig 1B that G3 and G4 are considered to be both electrically coupled to the first signal line or the second signal line).
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Regarding Claim 10, Liebmann et al discloses the limitations of claim 1 as explained above. Liebmann et al further discloses
wherein: the second transistor (P1 Fig 2A) and the fourth transistor (P2 Fig 2A) share a first common source/drain terminal (T2/T6 [page 7, lines 20-35] Fig 2A), and the first transistor (N1 Fig 2A) and the third transistor (N2 Fig 2A) share a second common source/drain terminal (T4/T8 [page 7, lines 20-35] Fig 2A).
Regarding Claim 11, Liebmann et al discloses the limitation of claim 1 as explained above. Liebmann et al further discloses
wherein the third transistor (N2 Fig 2A) is a first inactive transistor and the first transistor (N1 Fig 2A) is a second inactive transistor (P1 and N1 function as an open switch, P2 and N2 function as a closing switch [page 7, lines 1-7] Fig 2A, the examiner notes that inactive transistors of CFET are the transistors that are in the off state, which would be N1 and N2).
Regarding Claim 21, Liebmann et al discloses semiconductor device (2D semiconductor device 299 and 3D semiconductor device 399 [page 7, lines 1-23] Fig 2A-D and Fig 3A-L), comprising:
a first semiconductor layer (region 232 [page 7, lines 24 -35] Fig 2A) and a second semiconductor layer (region 231 [page 7, lines 24-35] Fig 2A) stacked vertically over a substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B); and
a first gate structure (conductive structure 211 [page 7, lines 36-46] Fig 2A) and a second gate structure (conductive structure 212 [page 7, lines 36-46] Fig 2A) extending vertically from the substrate (301 (not shown in Fig 2A-D) Fig 3A-B) and perpendicular to the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A),
the first gate structure (211 Fig 2A) engaging the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A) to form a first transistor (N1 [page 7, lines 12-19] Fig 2A) and a second transistor (P1 [page 7, lines 12-19] Fig 2A), respectively, and
the second gate structure (212 Fig 2A) engaging the first semiconductor layer (232 Fig 2A) and the second semiconductor layer (231 Fig 2A) to form a third transistor (N2 [page 7, lines 12-19] Fig 2A) and a fourth transistor (P2 [page 7, lines 12-19] Fig 2A), respectively,
wherein: the first gate structure (211 Fig 2A) is laterally adjacent to the second gate structure (212 Fig 2A),
the third transistor (N2 Fig 2A) is an inactive transistor (P1 and N1 function as an open switch, P2 and N2 function as a closing switch [page 7, lines 1-7] Fig 2A, the examiner notes that inactive transistors of CFET are the transistors that are in the off state, which would be N1 and N2), and the second transistor (P1 Fig 2A) and the fourth transistor (P2 Fig 2A) are active transistors (active channel space dh1 and dh2 [page 8, lines 30-50] Fig 2A).
Regarding Claim 22, Liebmann et al discloses the limitations of claim 21 as explained above. Liebmann et al further discloses
wherein the first (N1 Fig 2A) and third transistors (N2 Fig 2A) have a first conductive type (N-type), and the second (P1 Fig 2A) and fourth transistors (P2 Fig 2A) have a second conductive type (P-type).
Regarding Claim 23, Liebmann et al discloses the limitations of claim 21 as explained above. Liebmann et al further discloses
wherein: the third transistor (N2 Fig 2A) is coupled to a first source contact (T7 [page 7, lines 20-35] Fig 2A), a first drain contact (T8 [page 7, lines 20-35] Fig 2A), and a first gate contact (gate electrode G4 [page 7, lines 20-35] Fig 2A),
the fourth transistor (P2 Fig 2A) is coupled to a second gate contact (gate electrode G3 [page 7, lines 20-35] Fig 2A),
the first source contact (T7 Fig 2A) and the first drain contact (T8 Fig 2A) are both coupled to a first signal line (shown in annotated Fig 1B), and
the first gate contact (G4 Fig 2A) and the second gate contact (G3 Fig 2A) are both coupled to a second signal line (shown in annotated Fig 1B).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et al (TW 202121652) in view of Higuchi et al (US 4825274).
Regarding Claim 2, Liebmann et al discloses the limitations of claim 1 as explained above. Liebmann et al, as applied to claim 1, does not disclose
wherein: the first transistor and the third transistor are of p-type, the second transistor and the fourth transistor are of n-type, and the second semiconductor layer is disposed vertically between the first semiconductor layer and the substrate.
However, Higuchi et al, in the related art of semiconductor devices that include n-type and p-type CMOS transistors, discloses
wherein the p-type FET is changed to an n-type FET with similar effect [colum 5, lines 30-40].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liebmann et al to change the p-type FET transistors to n-type and the n-type FET transistors to p-type as taught by Uguchi et al in order invert the electron flow of the device with similar effect [column 5, lines 30-40], which is well known in the art. Further, a person of ordinary skill in the art would have recognized that changing the p-type FET transistors to n-type and the n-type FET transistors to p-type would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liebmann et al (TW 202121652) in view of Chen et al (US 2022/0359715).
Regarding Claim 8, Liebmann et al discloses the limitations of claim 1 as explained above. Liebmann et al does not disclose
further comprising a first dielectric structure and a second dielectric structure each extending vertically from the substrate and engaging with both the first semiconductor layer and the second semiconductor layer,
wherein the first gate structure and the second gate structure are disposed in a region between the first dielectric structure and the second dielectric structure.
Chen et al, in the related art of semiconductor devices that include FET devices, discloses
a first dielectric structure (first isolation structure 23 [0027] Fig 32 and Fig 33) and a second dielectric structure (second isolation structure 24 [0027] Fig 32 and Fig 33) each extending vertically from the substrate (semiconductor substrate 11 [0027] Fig 32 and Fig 33) and engaging with the semiconductor layers (semiconductor layers of the source/drain regions 17a and 17b [0024] Fig 32 and Fig 33) of the transistor (NMOS and PMOS transistors shown in Fig 32 and Fig 33);
wherein gate structures (poly gates 12a [0013] Fig 32 and Fig 33) are disposed in a region between the first dielectric structure (23 Fig 32 and Fig 33) and the second dielectric structure (24 Fig 32 and Fig 33).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Liebmann et al to include further comprising a first dielectric structure and a second dielectric structure each extending vertically from the substrate and engaging with both the first semiconductor layer and the second semiconductor layer, wherein the first gate structure and the second gate structure are disposed in a region between the first dielectric structure and the second dielectric structure as taught by Chen et al in order to improve the electrical performance as attributed to the isolation structures in a CPODE transistor [0028]. Further, a person of ordinary skill in the art would have recognized that having isolation structures would be advantageous in optimizing electrical functioning while avoiding damage due to undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Liebmann et al and Chen et al now discloses
further comprising a first dielectric structure (23 Fig 32 and Fig 33 Chen et al) and a second dielectric structure (24 Fig 32 and Fig 33 Chen et al) each extending vertically from the substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B Liebmann et al) and engaging with both the first semiconductor layer (region 232 [page 7, lines 24 -35] Fig 2A Liebmann et al) and the second semiconductor layer (region 231 [page 7, lines 24-35] Fig 2A Liebmann et al),
wherein the first gate structure (211 Fig 2A Liebmann et al) and the second gate structure (212 Fig 2A Liebmann et al) are disposed in a region between the first dielectric structure (23 Fig 32 and Fig 33 Chen et al) and the second dielectric structure (24 Fig 32 and Fig 33 Chen et al).
Allowable Subject Matter
Claims 12-17 are allowable.
Regarding Claim 12, Liebmann et al (TW 202121652) discloses a semiconductor device (2D semiconductor device 299 and 3D semiconductor device 399 [page 7, lines 1-23] Fig 2A-D and Fig 3A-L), comprising:
a first p-type transistor (P1 [page 7, lines 12-19] Fig 2A) and a first n-type transistor (N1 [page 7, lines 12-19] Fig 2A) stacked vertically over a substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B);
a second p-type transistor (P2 [page 7, lines 12-19] Fig 2A) and a second n-type transistor (N2 [page 7, lines 12-19] Fig 2A) stacked vertically over the substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B), the second p-type transistor (P2 Fig 2A) disposed laterally adjacent the first p-type transistor (P1 Fig 2A) and the second n-type transistor (N2 Fig 2A) disposed laterally adjacent the first n-type transistor (N1 Fig 2A); and
a first gate structure (gate structures G1 and G2 in row 255 [page 8, lines 8-20] Fig 2A) and a second gate structure (gate structures G3 and G4 in row 256 [page 8, lines 8-20] Fig 2A) extending from the substrate (substrate 301 (not shown in Fig 2A-D) [page 4, lines 30-45] Fig 3A-B) along a vertical direction,
the first p-type transistor (P1 Fig 2A) and the first n-type transistor (N1 Fig 2A) each including a portion of the first gate structure (G1 and G2 in row 255 Fig 2A), and
the second p-type transistor (P2 Fig 2A) and the second n-type transistor (N2 Fig 2A) each including a portion of the second gate structure (G3 and G4 in row 256 Fig 2A),
wherein: the first p-type transistor (P1 Fig 2A) and the second p-type transistor (P2 Fig 2A) are both coupled to a first source/drain contact (terminal T1, T2, T5, T6 [page 7, lines 20-35] Fig 2A),
the first n-type transistor (N1 Fig 2A) and the second n-type transistor (N2 Fig 2A) are both coupled to a second source/drain contact (terminal T3, T4, T7, T8 [page 7, lines 20-35] Fig 2A), and
the second p-type transistor (P2 Fig 2A) is an inactive transistor (active channel space dh1 and dh2 [page 8, lines 30-50] Fig 2A).
The reason for the indication of allowability of Claim 12 is the inclusion of
the second p-type transistor is a dummy transistor.
Specifically, although it would be obvious to include dummy semiconductor dies without electrical function when the electrical function is not desired and since it has been held that it would have been obvious to omit elements of the primary reference where the function attributed is not desired or required Ex parte Wu, 10 USPQ 2031 (Bd. Pat. App. $ Inter. 1989), it does not appear to be obvious to modify the device of Liebmann et al to include dummy semiconductor dies since it would teach away from the use of the transistors as switches with open and close functions, and a dummy unit would be a non-functioning unit.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 5-7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5:
Regarding Claim 5, Liebmann et al (TW 202121652) discloses the limitations of claim 1 as explained above. Liebmann et al (TW 202121652) further discloses
wherein: the third transistor (N2 Fig 2A) is coupled to a first source contact (T7 [page 7, lines 20-35] Fig 2A), a first drain contact (T8 [page 7, lines 20-35] Fig 2A), and a first gate contact (gate electrode G4 [page 7, lines 20-35] Fig 2A), and
the fourth transistor (P2 Fig 2A) is coupled to a second gate contact (gate electrode G3 [page 7, lines 20-35] Fig 2A) that is further coupled to a first signal line (shown in annotated Fig 1B).
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The reason for the indication of allowability of Claim 5 is the inclusion of
the first gate contact is coupled to power/ground.
Specifically, the ground GND is shown in Fig 1A of the reference Liebmann et al and the transistors cited here correspond to Fig 1B. Further, should another reference be found that discloses wherein the first gate contact is coupled to power/ground, it would not be obvious to a person of ordinary skill in the art to combine the references and alter Fig 1B of Liebmann et al to include a ground.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 6, 7, and 9 would be allowable based on their dependency on Claim 5.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Smith et al (US 10734224) which discloses a method of manufacturing that includes a substrate with a plurality of gate regions and a plurality of S/D regions [column 1, lines 35-65], and Shum et al (US 2003/0142541) which discloses a programmable cell with triple well structure wherein each cell has a floating gate transistor [0008]-[0009].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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