DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of invention Group I (claims 1-13 and 18-19), Species I (FIGs. 1-13) and Species A (FIG. 3) in the reply filed on 6/18/2026 is acknowledged. The traversal is on the ground(s) that (i) the process necessarily process the product claimed and (ii) there is no serious search burden since prior art disclosing the claimed device structure would naturally disclose its methods for manufacturing. This is not found persuasive. Regarding (i), inventions are distinct if the product as claimed can be made by another and materially different process (See MPEP § 806.05(f)). In the instance case, the device is made by etching the first epitaxial layer to form gate trenches and etching the interlayer dielectric layer to form contact hole as recited in claim 14. However, instead of the etching step, the gate trenches can be made by selective growth over a mask pattern and contact hole can be made by selective deposition through a mask pattern. As such, the product can be made by another materially different process and the inventions as claimed are distinct . Regarding (ii), there exist a serious search burden because the inventions require separate searches due to their different classification areas. Furthermore, search of the product would not require searching for the specific method steps, e.g. “epitaxially growing”, “etching” as recited in claim 14 and “ion implantation process as recited in claim 15.
The requirement is still deemed proper and is therefore made FINAL.
Applicant alleges claims 1-13 and 18-19 reads on the elected Species I (FIGs. 1-13) and Species A (FIG. 3). Upon further consideration, Examiner identifies claims 4, 8-9, and 12-13 as pertaining to non-elected Species. More specifically,
claim 4 reciting “a first gate trench and a second gate trench that communicate with each other in the first direction, and the first gate trench and the second gate trench are respectively located in two adjacent trench groups” pertains to a feature shown in FIG. 22 (¶ 227), corresponding to non-elected Species B
claims 8-9 reciting “the fifth P-type semiconductor region is disposed on a side of the a side wall of the gate trench and not disposed with a third P-type semiconductor region” pertains to a feature shown in FIGs. 16-18 (¶ 207), corresponding to non-elected Species III
claims 12-13 reciting “a second epitaxial layer is disposed between the first epitaxial layer and the N-type semiconductor substrate, and a doping concentration of the second epitaxial layer is less than a doping concentration of a first N-type semiconductor region of the first epitaxial layer; and a thickness of the second epitaxial layer in the third direction is greater than 1 µm” pertains to a feature shown in FIG. 23 (¶ 232-233), corresponding to non-elected Species V
Therefore, claims 4, 8-9, and 12-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/18/2026.
Drawings
The drawings are objected to because numerous inconsistency present across different figures.
Region 5 is depicted as “P+” in FIGs. 8-9, 13d-13j, 14-21, 23, but is depicted as “P-“ in FIGs. 4 & 7.
Region 6 is depicted as “N+” in FIGs. 5-6, 8-9, 11, 13d-13j, 14-21, 23, but is depicted as “N-“ in FIG. 7.
Region 8 is depicted as “P+” in FIGs. 5-6, 10-11, 13b, but is depicted as “P-“ in FIGs. 4, 7-9, 13d-j, 14-21, 23
Region 9 is depicted as “P+” in FIG. 7, but is depicted as “P-“ in FIGs. 4, 8-9, 13f-j, 14, 16-21, 23
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-7, 10-11, and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “the first gate … spaced apart by a gate dielectric layer” and “the second gate … is spaced apart by a gate dielectric layer” render the claim indefinite. It is unclear what are the first gate and the second gate spaced apart from.
Claim 2 reciting “the plurality of gate trenches are divided into at least one trench group, and there are at least two contact holes; and the one trench group is disposed between two adjacent contact holes, and the contact hole spans across the trench group in the second direction” renders the claim indefinite due to unclear antecedent basis. Claim 1 previously recite one “contact hole”. Claim 2 recite recites “at least two contact holes”, “two adjacent contact holes”, and “the contact hole”. It is unclear how many contact holes are required due to inconsistent recitations. Furthermore, it is unclear if the “at least two contact holes” are intended to be in addition to the “contact hole” recited in claim 1 or if the “contact hole” in claim 1 covered by “at least two contact holes”. Furthermore, recitations to “at least one the trench group”, “the one trench group”, and “the trench group” are inconsistent. It is unclear how many trench groups are required.
Claim 2 reciting “the contact hole spans across the trench group in the second direction” renders the claim indefinite. The contact hole and the gate trenches are offset from each other. They are arranged side-by-side as shown in Applicant’s FIG. 3. It is unclear how would the contact hole “spans across” the trench group.
Claim 3 reciting “different trench groups” renders the claim indefinite due to unclear antecedent basis. Claim 2 previously recite “at least one trench group” encompassing one trench group only. It this case, it is unclear what is intended by “different trench groups”.
Claim 5 reciting “the gate trench” renders the claim indefinite. Claim 1 previously recite “a plurality of gate trenches”. It is unclear “the gate trench” in claim 5 is intended to refer to one of the plurality of gate trenches or each of the plurality of gate trenches.
Claim 5 reciting “source regions” and “the source region” renders the claim indefinite due to unclear antecedent basis. It is unclear “the source region” is intended to refer to one of the source regions or each of the source regions.
Claim 6 reciting “the gate trench” renders the claim indefinite. Claim 1 previously recite “a plurality of gate trenches”. It is unclear “the gate trench” in claim 6 is intended to refer to one of the plurality of gate trenches or each of the plurality of gate trenches.
Claim 6 reciting “a second P-type semiconductor region” render the claim indefinite. No “first P-type semiconductor region” has been recited previously in claims 1 or 6. It is unclear if the “second P-type semiconductor region” implies presence of a “first P-type semiconductor region.
Claim 7 reciting “the gate trench” and “at least one gate trench” renders the claim indefinite. Claim 1 previously recite “a plurality of gate trenches”. It is unclear “the gate trench” or “at least one gate trench” in claim 7 is intended to refer to one of the plurality of gate trenches, each of the plurality of gate trenches, or some of the plurality of gate trenches.
Claim 7 recites “the gate trench has a first side wall and a second side wall” and “a first sidewall and/or a second side wall of at least one gate trench” render the claim indefinite. It is unclear if the “first side wall” recited are intended to be the same. It is also unclear if the “second sidewall” recited are intended to be the same.
Claim 10 reciting “the gate trench” renders the claim indefinite. Claim 1 previously recite “a plurality of gate trenches”. It is unclear “the gate trench” in claim 10 is intended to refer to one of the plurality of gate trenches or each of the plurality of gate trenches.
Claim 11 reciting “two adjacent gate trenches” renders the claim indefinite. It is unclear if these are intended to refer to “the plurality of gate trenches” previously claimed or are additional gates.
Claim 18 reciting “the first gate … spaced apart by a gate dielectric layer” and “the second gate … is spaced apart by a gate dielectric layer” render the claim indefinite. It is unclear what are the first gate and the second gate spaced apart from.
Claim 18 reciting “each one of the one more semiconductor devices” renders the claim indefinite. It is unclear what is intended by “the one more semiconductor devices”.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hagino et al. JP 2019-21871 (Hagino).
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In re claim 1, as best understood, Hagino discloses (e.g. FIGs. 1-4) a semiconductor device, comprising:
an N-type semiconductor substrate 11;
a first epitaxial layer (semiconductor body above 11), wherein the first epitaxial layer is disposed on the semiconductor substrate 11;
a plurality of gate trenches 16 disposed at intervals, wherein
the plurality of gate trenches 16 extend to the first epitaxial layer (semiconductor body above 11) in a third direction (vertical thickness direction in FIGs. 2-4) perpendicular to a plane (horizontal plane) on which the semiconductor substrate 11 is located;
the plurality of gate trenches 16 extend in a first direction (lateral direction in FIG. 1) parallel to the plane on which the semiconductor substrate 11 is located; and
the plurality of gate trenches 16 are arranged in a second direction (longitudinal direction in FIG. 1) parallel to the plane on which the semiconductor substrate 11 is located, wherein the first direction (lateral direction in FIG. 1), the second direction (longitudinal direction in FIG. 1), and the third direction (vertical thickness direction in FIGs. 2-4) are set in a cross manner;
a gate 18+19 comprising a first gate 18 and a second gate 19 that are in contact with each other (see FIG. 3), wherein the first gate 18 is filled and disposed in a gate trench 16 of the plurality of gate trenches 16 and is “spaced apart” by a gate dielectric layer 17 (as best understood, spaced apart from epitaxial layer, see FIG. 3), and wherein the second gate 19 is disposed on top of the first epitaxial layer and is “spaced apart” by the gate dielectric layer 17 (spaced apart from epitaxial layer, see FIG. 3);
an interlayer dielectric layer 20 that covers a side (top side) of the gate 18+19 that is away from the semiconductor substrate 11, wherein the interlayer dielectric layer 20 comprises a contact hole 21 that extends in the second direction (contact hole 21 is three dimensional and extends in all direction including the second direction corresponding to the longitudinal direction in FIG. 1), an orthographic projection of the contact hole 21 on the semiconductor substrate 11 does not overlap an orthographic projection of the gate 18+19 on the semiconductor substrate 11 (see FIGs. 2 & 4), and the contact hole 21 exposes a partial region of the first epitaxial layer (contact hole 21 exposes N+ region 15 and P region 13 in the epitaxial layer);
a source 23b that is disposed on a side of the interlayer dielectric layer 20 and away from the semiconductor substrate 11, wherein the source 23b is in contact, through the contact hole 21, with the first epitaxial layer exposed by the contact hole (23b contacting N+ region 15 and P region 13 in the epitaxial layer); and
a drain 25 that is disposed on a side (bottom side) of the semiconductor substrate 11 and away from the first epitaxial layer.
In re claim 2, as best understood, Hagino discloses (e.g. FIGs. 1-2) wherein
the plurality of gate trenches 16 are divided into “at least one trench group” (e.g. the group of six trenches 16 in FIG. 2), and there are “at least two contact holes” (e.g. leftmost contact hole 21 and rightmost contact hole 21 in FIG. 2); and
“the one trench group” is disposed between two adjacent contact holes (group of six trenches between leftmost contact hole 21 and rightmost contact hole 21 that are considered to be “adjacent” understood to mean “close to”, no specific proximity is required for “adjacent”), and “the contact hole” (leftmost contact hole 21 and rightmost contact hole 21) “spans across the trench group in the second direction” (as best understood, leftmost contact hole 21 and rightmost contact hole 21 define a spacing distance in between that spans across the group of all six trenches in the arrangement direction of the trenches corresponding to the second direction).
In re claim 3, as best understood, Hagino discloses (e.g. FIG. 2) wherein quantities of “gate trenches” 16 in different trench groups are the same (e.g. a group of three trenches 16 on the left and a group of three trenches 16 on the right, each between a contact hole 21 to the left of the three trenches and a contact hole 21 to the right of the three trenches, the contact holes are “adjacent” or “close to” each other).
In re claim 5, as best understood, Hagino discloses (e.g. FIGs. 2 & 4) wherein
the first epitaxial layer (semiconductor body above 11) comprises a first N-type semiconductor region (lower portion of 12), a second N-type semiconductor region (upper portion of 12), a first P-type semiconductor region 13, and source regions 15, wherein the first N-type semiconductor region (lower portion of 12) is disposed between the second N-type semiconductor region (upper portion of 12) and the semiconductor substrate 11, the first P-type semiconductor region 13 is disposed on a side of the second N-type semiconductor region (upper portion of 12) and that is away from the semiconductor substrate 11, and “the source region” 15 is disposed on a side of the first P-type semiconductor region 13 and away from the semiconductor substrate 11;
the gate trench 16 extends to the first N-type semiconductor region (lower portion of 12 encompassing bottom of trenches 16) in the third (vertical) direction perpendicular to the plane on which the semiconductor substrate 11 is located; and
the contact hole 21 exposes a partial region of “the source region” 15 (sidewalls of source regions 15 exposed by contact hole 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hagino et al. JP 2019-21871 (Hagino) as applied to claim 1 above, and further in view of Iwahashi et al. JP 2021-34621 A (Iwahashi).
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In re claim 6, Hagino discloses the claimed invention including a power MOSFET comprising gate trenches 16 connecting into the drift layer 12.
Hagino does not explicitly teach wherein the first epitaxial layer further comprises: “a second P-type semiconductor region” (as best understood) that is disposed below “the gate trench” (as best understood) and connected to the source.
However, Iwahashi teaches (FIGs. 1-3) a power MOSFET comprising a drift layer 22, gate trenches extending into the drift layer 22 and further comprising “a second P-type semiconductor region” 23 that is disposed below “the gate trench” 40,50 and connected to the source 34 (connected through 28). Iwahashi discloses the P-type semiconductor region 23 covering the bottoms of the trench gates 40,50 to alleviate electric field concentration on the bottom of the trench gates and obtain a device with high withstand voltage.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form P-type semiconductor region below Hagino’s gate trenches 16 and connect to the source 23 to relax electric field at the bottom of the gate trenches to ensure high withstand voltage as taught by Iwahashi.
In re claim 7, as best understood, Iwahashi discloses (e.g. FIGs. 3) wherein in the first direction (y-direction), “the gate trench” 50 has a first (left) side wall and a second (right) side wall that are disposed opposite to each other; and
the first epitaxial layer (semiconductor body 20 above 21) further comprises:
a third P-type semiconductor region 28 that is disposed on “a first (left) side wall” and/or “a second (right) side wall” of “at least one gate trench” 50, and the third P-type semiconductor region 28 is in contact with the second P-type semiconductor region 23; and
a fourth P-type semiconductor region 26, wherein the fourth P-type semiconductor region 26 and a source region 27 are disposed at a same layer, the fourth P-type semiconductor region 26 is disposed on a side of the third P-type semiconductor region 28 and away from “the gate trench” 50, the fourth P-type semiconductor region 26 is in contact with the third P-type semiconductor region 28 (through p region 25), and the fourth P-type semiconductor region 26 is in contact with the source 34 through the contact hole (hole through dielectric above gate 54).
In re claim 10, as best understood, Iwahashi discloses (e.g. FIG. 3) wherein an orthographic projection of the second P-type semiconductor region 23 on the semiconductor substrate covers an orthographic projection of “the gate trench” 50 on the semiconductor substrate and an orthographic projection of the third P-type semiconductor region 28 on the semiconductor substrate (portion of p region 23 below gate 50 and sidewall portion 28).
In re claim 11, as best understood, Iwahashi discloses (e.g. FIGs. 1-3) wherein
the second P-type semiconductor region 23 is a planar region (planar portion below gate 50) extending in the second (y) direction; and
the orthographic projection of the second P-type semiconductor region 23 on the semiconductor substrate further covers a gap between orthographic projections of “two adjacent gate trenches” 40,50 on the semiconductor substrate (p-type region 23 overlaps at least a portion of the gap between adjacent gates 40,50).
Claims 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hagino et al. JP 2019-21871 (Hagino) in view of Adachi et al. US 2020/0194554 A1 (Adachi).
In re claim 18, as best understood, Hagino discloses (e.g. FIGs. 1-4) one or more semiconductor devices, each one of the one more semiconductor devices comprising:
an N-type semiconductor substrate 11;
a first epitaxial layer (semiconductor body above 11), wherein the first epitaxial layer is disposed on the semiconductor substrate 11;
a plurality of gate trenches 16 disposed at intervals, wherein
the plurality of gate trenches 16 extend to the first epitaxial layer (semiconductor body above 11) in a third direction (vertical thickness direction in FIGs. 2-4) perpendicular to a plane (horizontal plane) on which the semiconductor substrate 11 is located;
the plurality of gate trenches 16 extend in a first direction (lateral direction in FIG. 1) parallel to the plane on which the semiconductor substrate 11 is located; and
the plurality of gate trenches 16 are arranged in a second direction (longitudinal direction in FIG. 1) parallel to the plane on which the semiconductor substrate 11 is located, wherein the first direction (lateral direction in FIG. 1), the second direction (longitudinal direction in FIG. 1), and the third direction (vertical thickness direction in FIGs. 2-4) are set in a cross manner;
a gate 18+19 comprising a first gate 18 and a second gate 19 that are in contact with each other (see FIG. 3), wherein the first gate 18 is filled and disposed in a gate trench 16 of the plurality of gate trenches 16 and is “spaced apart” by a gate dielectric layer 17 (as best understood, spaced apart from epitaxial layer, see FIG. 3), and wherein the second gate 19 is disposed on top of the first epitaxial layer and is “spaced apart” by the gate dielectric layer 17 (spaced apart from epitaxial layer, see FIG. 3);
an interlayer dielectric layer 20 that covers a side (top side) of the gate 18+19 that is away from the semiconductor substrate 11, wherein the interlayer dielectric layer 20 comprises a contact hole 21 that extends in the second direction (contact hole 21 is three dimensional and extends in all direction including the second direction corresponding to the longitudinal direction in FIG. 1), an orthographic projection of the contact hole 21 on the semiconductor substrate 11 does not overlap an orthographic projection of the gate 18+19 on the semiconductor substrate 11 (see FIGs. 2 & 4), and the contact hole 21 exposes a partial region of the first epitaxial layer (contact hole 21 exposes N+ region 15 and P region 13 in the epitaxial layer);
a source 23b that is disposed on a side of the interlayer dielectric layer 20 and away from the semiconductor substrate 11, wherein the source 23b is in contact, through the contact hole 21, with the first epitaxial layer exposed by the contact hole (23b contacting N+ region 15 and P region 13 in the epitaxial layer); and
a drain 25 that is disposed on a side (bottom side) of the semiconductor substrate 11 and away from the first epitaxial layer.
Hagino discloses a power MOSFET for handing high voltage. Hagino does not explicitly disclose employing the power MOSFET in a power conversion circuit comprising a circuit board; and connecting the power MOSFET to the circuit board.
Adachi discloses a power conversion unit 201 (see FIG. 32) comprising a circuit board (not shown, support to which the power converter 200 is mounted on and to electrically couple to larger scale electric equipment, ¶ 168), one or more power semiconductor devices (see FIG. 1, ¶ 166) connected to the circuit board. Adachi discloses using the power MOSFET as switching element in power conversion circuit is known (¶ 166) for the high power handling capability of the power MOSFET and obtain power converter with reduced power loss (¶ 166,173).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Hagino’s power MOSFET in a power conversion circuit to handle high voltage and form a power converter with reduced power loss as taught by Adachi.
In re claim 19, Adachi discloses a vehicle (¶ 168), comprising the power conversion circuit 201 (e.g. FIG. 32) according to claim 18, wherein the power conversion circuit is configured to convert an alternating current and/or a direct current and output a direct current (¶ 167).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5321289 teaches (FIGs. 1-2) trench gates 14 connected by planar gate connector.
US 6285058 teaches (FIGs. 1-4) trench gates 7 connected by planar gate connector 9.
US 6380586 teaches (FIG. 15-16) auxiliary gate 13 connecting trench gates 10.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights