DETAILED ACTION
Specification
The disclosure is objected to because of the following informalities: Paragraph 48 of the specification recites the following:
“In some embodiments, the thickness of the high-k dielectric layer 127 is between about 3 nm and 10 nm. In some embodiments, a first combined thickness of the gate silicon oxide layer 125 and the high-k dielectric layer 127 is less than a second combined thickness of the gate silicon oxide layer 115 and the high-k dielectric layer 117 in the transistor 120 or a third combined thickness of the gate silicon oxide layer 105 and the high-k dielectric layer 107 in the transistor 110 described above. In some embodiments, the first combined thickness is at least 20%, 40%, or 50% less than the second or third combined thicknesses”.
This information is contradictory to what is present in paragraph 6 of the specification, as well as claims 1, 13 and 18 of the application. The first combination thickness as a thickness associated with the planar-type transistors or FinFET and the second combination thickness as a thickness associated with the GAA transistor. However, the first combined thickness as taught in paragraph 48 is applied to the GAA transistor and the second combined thickness is applied to the planar-type transistors or FinFET. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-13 and 17-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Majhi et al. (US 2023/0086977 A1; hereinafter “Majhi”).
In regard to claim 1, Majhi teaches a semiconductor structure (IC device 200) (Fig. 2 and paragraph 39), comprising:
a first substrate (a FinFET layer 130) including a plurality of first-type transistors formed of planar-type transistors or fin-type transistors (the FinFET layer 130 contains FinFETs 230) (Fig. 2, paragraphs 29 and 41), wherein a gate silicon oxide layer of each of the planar-type transistors has a first thickness, and a gate silicon oxide layer (gate dielectric material 252) of each of the fin-type transistors has a second thickness (the gate dielectric material 252 is shown in Fig. 2) (Fig. 2 and paragraphs 42 and 50) ; and
a second substrate (GAA transistor layer 120) bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors (the GAA transistor layer 120 may be a layer in which a plurality of GAA transistors 220 may be implemented and may be front end of line (FEOL) transistors) (Fig. 2, paragraphs 31-32), wherein a gate silicon oxide layer (gate dielectric material 252) of each of the GAA transistors has a third thickness (Fig. 2 and paragraph 47),
wherein the third thickness is less than the first thickness or the second thickness (the architecture of FinFETs allows including thicker gate dielectrics in the gate stacks of the transistors compared to gate dielectrics that may be included in GAA transistors) (paragraph 32).
In regard to claim 2, Majhi teaches wherein the third thickness is less than about 1 nm (the gate dielectric material 252 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein) (paragraph 50).
In regard to claim 3, Majhi teaches wherein the second thickness is substantially equal to or greater than about 1.5 nm (the gate dielectric material 252 may have a thickness between about 0.5 nanometers and 3 nanometers, including all values and ranges therein) (paragraph 50).
In regard to claim 4, Majhi teaches wherein the first thickness is substantially equal to or greater than about 1.8 nm (only the FinFET was considered for independent claim 1).
In regard to claim 5, Majhi teaches wherein the first-type transistors operate under a first voltage (High voltage) (paragraph 18), and the second-type transistors operate under a second voltage (low voltage) less than the first voltage (the architecture of FinFETs allows including thicker gate dielectrics in the gate stacks of the transistors compared to gate dielectrics that may be included in GAA transistors, which allows realizing relatively high-voltage transistors based on FinFETs (“high-voltage”) compared to what can be realized with the GAA transistors) (paragraphs 18 and 50).
In regard to claim 6, Majhi teaches the semiconductor structure, further comprising:
a bonding (a device layer 2106) structure between the first substrate and the second substrate (as the transistors 2140 may include the GAA transistors 220 and the FinFETs integrated over GAA transistors as described herein may be implemented in any of the interconnect layers 2106-2110 the device layer 2106 would serve as a bonding layer between a FinFET on the device layer 2108 and the GAA) (Fig. 2, Fig. 7 and paragraphs 63 and 65), wherein the first-type transistors and the second-type transistors are interconnected to allow a power signal or an electrical signal inputted from an input terminal to arrive at the second-type transistors by first passing the bonding structure (interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220) (paragraph 43). Furthermore, regarding the claim language that states “interconnected to allow a power signal or an electrical signal inputted from an input terminal to arrive at the second-type transistors by first passing the bonding structure”, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987).
If the prior art structure is capable to performing the intended use, and then it meets the claim, there as the interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220 the claim is met.
In regard to claim 9, Majhi teaches a through substrate via (TSV) (interconnect structures 2128 ) in at least one of the first substrate and the second substrate, and electrically connected to the bonding structure (the interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals) (Fig. 7 and paragraphs 73-74).
In regard to claim 10, Majhi teaches wherein the bonding structure comprises one of a hybrid bonding layer (interconnect layer 2106 contains trench structures 2128A and therefore would facilitate hybrid bonding layer having metal to metal and dielectric to dielectric contact points) (Fig. 7 and paragraph 74), an under bump metallization, a conductive bump, or a micro bump.
In regard to claim 11, Majhi teaches wherein the second-type transistors form a processor for artificial intelligence (AI) machine-learning or AI deep-learning applications (a processing device 2402 is formed from the use of the GAA transistors) (paragraph 99). Further, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim.
In regard to claim 12, Majhi teaches wherein the second substrate comprises at least one of an I/O circuit, an analog circuit, a power circuit and a memory circuit (the GAA transistor layer 120 may be used to implement one or more of I/O circuitry) (paragraph 31).
In regard to claim 13, Majhi teaches a semiconductor device(IC device 200) (Fig. 2 and paragraph 39), comprising:
a first substrate (a FinFET layer 130) including a plurality of first-type transistors formed of planar-type transistors or fin-type transistors (the FinFET layer 130 contains FinFETs 230) (Fig. 2, paragraphs 29 and 41), wherein the first-type transistors operate under a first voltage (high voltage) and wherein each of the plurality of first-type transistors has a first gate silicon oxide layer (gate dielectric material 252) stacking with a first high-k dielectric layer (the FinFET 230 operates under a high voltage and contains gate dielectric material 252 formed of hafnium silicon oxide stacked with the FE/AFE material 416 formed of hafnium zirconium oxide (HZO) ) (Fig. 2, Fig. 4B and paragraphs 18, 50, 54 and 56), the first gate silicon oxide layer and the first high-k dielectric layer having a first combined thickness (a combined thickness is shown in Fig. 4B); and
a second substrate (GAA transistor layer 120) bonded to the first substrate and including a plurality of second-type transistors formed of gate-all-around (GAA) transistors (the GAA transistor layer 120 may be a layer in which a plurality of GAA transistors 220 may be implemented and may be front end of line (FEOL) transistors) (Fig. 2, paragraphs 31-32 and 40), wherein the second-type transistors operate under a second voltage (low voltage) less than the first voltage and wherein each of the plurality of second-type transistors has a second gate silicon oxide layer stacking with a second high-k dielectric layer (the GAA transistors 220 operates under a low voltage and contains gate dielectric material 252 formed of hafnium silicon oxide stacked with the FE/AFE material 416 formed of hafnium zirconium oxide (HZO) ) (Fig. 2, Fig. 4B and paragraphs 18, 50, 54 and 56), the second gate silicon oxide layer and the second high-k dielectric layer having a second combined thickness,
wherein the first combined thickness is greater than the second combined thickness (the architecture of FinFETs allows including thicker gate dielectrics in the gate stacks of the transistors compared to gate dielectrics that may be included in GAA transistors) (paragraph 32).
In regard to claim 17, Majhi teaches wherein at least one of the first substrate and the second substrate comprises a TSV electrically coupled to the other of the first substrate and the second substrate (the interconnect structures 2128 may be arranged within the interconnect layers 2106-1210 to route electrical signals) (Fig. 7 and paragraphs 73-74).
In regard to claim 18, Majhi a method (a fabrication method 500), comprising:
forming a plurality of first die regions (dies 2002 that may include one or more FinFETs) on a first semiconductor wafer (a FinFET layer 130 may include performing a layer transfer of a substantially single-crystalline semiconductor material grown on another support structure to be over the GAA transistor layer 120) (paragraph 32),
wherein each of the first die regions comprises a plurality of first-type transistors formed of planar-type transistors or fin-type transistors (the FinFET layer 130 is comprised of FinFETs 230) (paragraph 41), wherein a gate silicon oxide layer of each of the planar-type transistors has a first thickness, and a gate silicon oxide layer (gate dielectric material 252) of each of the fin-type transistors has a second thickness (the gate dielectric material 252 is shown in Fig. 2) (Fig. 2 and paragraphs 42 and 50); forming a plurality of second die regions (dies 2002 that may include one or more GAA transistors) on a second semiconductor wafer (a support structure 110 that contains the GAA transistor layer 120 before assembly) (paragraph 60), wherein each of the second die regions comprises a plurality of second-type transistors formed of gate-all-around (GAA) transistors (GAA transistors 220 are formed in the GAA transistor layer 120) (paragraph 40), wherein a gate silicon oxide layer (gate dielectric material 252) of each of the GAA transistors has a third thickness (a thickness of the gate dielectric material 252 is shown in Fig. 2) (Fig. 2 and paragraph 47); and
bonding the first semiconductor wafer to the second semiconductor wafer by electrically coupling each of the first die regions to a corresponding one of the second die regions (the method 500 may further include a process 504, that includes performing a layer transfer to provide a FinFET layer over the GAA transistor layer where interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220) (paragraph 43 and 60), wherein the third thickness is less than the first thickness or the second thickness (the architecture of FinFETs allows including thicker gate dielectrics in the gate stacks of the transistors compared to gate dielectrics that may be included in GAA transistors) (paragraph 32).
In regard to claim 19, Majhi teaches forming through-substrate vias (TSVs) in a first interconnection area of the first semiconductor wafer prior to bonding (The GAA transistor layer provided in the process 502 may include any embodiments of the GAA transistor layer 120 and therefore would include the interconnect structures 2128 prior to bonding) (paragraphs 60 and 73-74).
In regard to claim 20, Majhi teaches prior to bonding the first semiconductor wafer to the second semiconductor wafer, further comprising: forming a portion of a bonding structure (a bonding interface) at a front side or a back side of the first semiconductor wafer (paragraph 60); and forming a portion of the bonding structure at a front side or a back side of the second semiconductor wafer (a bonding interface may be detectable between the GAA transistor layer provided in the process 502 and the semiconductor material transferred in the process 504) (paragraph 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi as applied to claim 1 or 13 above.
In regard to claim 7, Majhi doesn’t explicitly teach wherein the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electrical signal inputted from the input terminal to arrive at the second-type transistors by entering the first-type transistors prior to passing the bonding structure. However, interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220 therefore the Examiner takes official notice that the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electrical signal inputted from the input terminal to arrive at the second-type transistors by entering the first-type transistors prior to passing the bonding structure. Furthermore, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim.
In regard to claim 8, Majhi doesn’t explicitly teach wherein the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electrical signal outputted from the second-type transistors to an output terminal to arrive at the output terminal by first passing the bonding structure. However, interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220 therefore the Examiner takes official notice that the first-type transistors and the second-type transistors are further interconnected to allow the power signal or the electrical signal outputted from the second-type transistors to an output terminal to arrive at the output terminal by first passing the bonding structure. Furthermore, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim.
In regard to claim 14, Majhi teaches wherein the second voltage is supplied to the second-type transistors through the first-type transistors and passing a bonding structure (a device layer 2106) between the first substrate and the second substrate (as the interconnects couple one or more of the FinFETs 230 and one or more of the GAA transistors 220 through the device layer 2106 and GAA transistors may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, the Examiner takes official notice that it would’ve been obvious to one skilled in the art that the second voltage is supplied to the second-type transistors through the first-type transistors and passing a bonding structure) (paragraphs 18 and 43).
In regard to claim 15, Majhi teaches wherein the bonding structure comprises one of a hybrid bonding layer (interconnect layer 2106 contains trench structures 2128A which functions as a hybrid bonding layer) (Fig. 7 and paragraph 74), an under bump metallization, a conductive bump, or a micro bump.
In regard to claim 16, Majhi teaches wherein the second combined thickness is less than the first combined thickness by at least 50% of the first combined thickness (The architecture of FinFETs allows including thicker gate dielectrics in the gate stacks of the transistors compared to gate dielectrics that may be included in GAA transistors, which allows realizing relatively high-voltage transistors based on FinFETs (“high-voltage” compared to what can be realized with the GAA transistors. Therefore, the examiner takes official notice that it would’ve been obvious to one skilled in the art to have the second combined thickness is less than the first combined thickness by at least 50% of the first combined thickness).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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