Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restriction
Applicant’s election with traverse of invention I (claims 1-10) in the reply filed on 08/26/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/23/2024, 03/26/2025 and 09/04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 9-10 are objected to because of the following informalities:
Claim 9, line 2: “storage layers” should read “charge storage units”.
Claim 10 is objected to by virtue of its dependency on claim 9.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US20210104535A1; Yang et al.; (hereinafter “Yang”) in view of US9236392B1; Izumi et al.; (hereinafter “Izumi”).
Regarding Claim 1, Yang teaches a memory device ([0003]), comprising:
a composite stacked structure (Figure 3E, [0055]), comprising:
a first stacked structure (#120), comprising a plurality of insulating layers (#124) and a plurality of conductive layers (#170) stacked alternately, over a first region (memory region);
a channel pillar (#160-164), extending through the first stacked structure (#120);
a plurality of charge storage units (#190), embedded in the first stacked structure (#120), and between the channel pillar (#160-164) and the plurality of conductive layers (#170);
a tunneling layer (#150), disposed between the channel pillar (#160-164) and the plurality of charge storage units (#190); and
at least one blocking layer (#130) disposed between the plurality of charge storage units (#190) and the plurality of conductive layers (#170),
wherein a thickness of one of the plurality of the charge storage units is greater than a thickness of a corresponding conductive layer ([0059], height H of #190 is greater than thickness T1 of #170).
Yang does not explicitly teach a second stacked structure, comprising the plurality of insulating layers and a plurality of intermediate layers stacked alternately, over a second region.
However, Izumi teaches a memory structure (col. 1, ln. 22-35), comprising a second stacked structure (Figure 15, alternating stack #32-42 in region #200), comprising the plurality of insulating layers (#32, insulators) and a plurality of intermediate layers (#42, sacrificial layers) stacked alternately, over a second region (#200, peripheral region).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Yang with the teaching of Izumi in order to provide peripheral device in peripheral region that support the operation of devices in memory array region according to Izumi, col. 5, ln. 58-62.
Regarding Claim 2, Yang in view of Izumi teaches the memory device as described in claim 1, wherein Yang further teaches a plurality of high-k dielectric layers (#172, Figure 3E), disposed between the at least one blocking layer (#130) and the plurality of conductive layers (#170).
Regarding Claim 3, Yang in view of Izumi teaches the memory device as described in claim 2, wherein Yang further teaches the thickness (#H) of one of the plurality of charge storage units (#190, Figure 3E) is less than a sum of the thickness (#T1) of the corresponding conductive layer (#170) and twice a thickness of the corresponding high-k dielectric layer ([0059], height H of #190 is substantially equal to a total of thickness T1 of #170 and twice thickness T2 of layer #130 or thickness of layer #172 since height H of #190 is substantially equal to a total thickness of layers #130, #172 and #170. According to [0038], a substantial dimension of elements as described may include a reasonable of +/- 20% value as understood by one of ordinary skill in the art, hence, height of #190 can reasonably have a value less than a total of thickness of #170 and twice thickness of #130/#172).
Regarding Claim 4, Yang in view of Izumi teaches the memory device as described in claim 2.
Yang does not explicitly teach a thickness of one of the plurality of intermediate layers is greater than a sum of the thickness of the corresponding conductive layer and twice a thickness of the corresponding high-k dielectric layer.
However, Izumi teaches a thickness of one of the plurality of intermediate layers is greater than a sum of the thickness of the corresponding conductive layer and twice a thickness of the corresponding high-k dielectric layer (Yang teaches that the thickness of the charge storage unit is less than a total thickness of the conductive layer and twice the high-k dielectric layer, see rejection of claim 3. According to Izumi, col. 7, ln. 13-16 and col. 9, ln. 40-42, thicknesses of sacrificial layer #42 and charge storage layer can be 20-50 nm and 2-20 nm respectively. Hence, the thickness of sacrificial layer #42 in peripheral region #200 is greater than a total thickness of the conductive layer and twice the high-k dielectric layer.
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Yang with the teaching of Izumi for reason set forth in rejection of claim 1.
Regarding Claim 5, Yang in view of Izumi teaches the memory device as described in claim 2, wherein Yang further teaches a ratio of a sum of the thickness of one of the plurality of conductive layers and twice a thickness of the corresponding high-k dielectric layer to a thickness of the corresponding intermediate layer is 0.7 to 0.8. (Yang in view of Izumi teaches the thickness of sacrificial layer #42 in peripheral region #200 is greater than the thickness of the charge storage layer or the total thickness of the conductive layer and twice the high-k dielectric layer, see rejection of claim 4. Izumi, col. 7, ln. 13-16 and col. 9, ln. 40-42, teaches thicknesses of charge storage layer and sacrificial layer #42 can be, for instance, 20 nm and 30 nm respectively. Hence, a ratio between the thicknesses is about 0.7).
Regarding Claim 6, Yang in view of Izumi teaches the memory device as described in claim 2, wherein Yang further teaches a thickness of one of the plurality of intermediate layers is greater than the thickness of the corresponding charge storage unit (see rejection of claim 4 or 5, Izumi teaches col. 7, ln. 13-16 and col. 9, ln. 40-42, thicknesses of sacrificial layer #42 and charge storage layer can be 20-50 nm and 2-20 nm respectively).
Regarding Claim 7, Yang in view of Izumi teaches the memory device as described in claim 2, wherein Yang further teaches a first distance between two adjacent charge storage units is greater than a second distance between two adjacent high-k dielectric layer (height H of charge storage layer #190 can reasonably have a value substantially less than a total thickness of corresponding conductive #170 and twice layer #130/#172, see rejection of claim 3, hence, the distance between #190 is greater than distance between #130/172).
Regarding Claim 8, Yang in view of Izumi teaches the memory device as described in claim 7, wherein Yang further teaches the second distance is greater than a third distance between two adjacent intermediate layers (the distance between adjacent charge storage layers #190 is greater than the distance between adjacent layer #130/170, see rejection of claim 7, and since the thickness of intermediate layer is much greater than the thickness of corresponding charge storage layer, see rejection of claim 6, therefore, the distance between adjacent charge storage layers, or adjacent high-k dielectric layers, is much greater than the distance between adjacent intermediate layers).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Izumi, and further in view of US 20230299182A1; Jun Noh Lee; (hereinafter “Lee”).
Regarding Claim 9, Yang in view of Izumi teaches the memory device as described in claim 1, wherein Yang further teaches the at least one blocking layer comprises a plurality of second blocking layers (#130, Figure 3E) disposed between the charge storage units (#190) and the plurality of conductive layers (#170).
Yang in view of Izumi does not explicitly teach a first blocking layer disposed between the plurality of storage layers and the plurality of conductive layers, and the plurality of second blocking layers disposed between the first blocking layer and the plurality of conductive layers.
However, Lee teaches a memory structure ([0009]), comprising a first blocking layer (#26, Figures 4A-B or 5A-E, [0065], blocking dielectric layer) disposed between a plurality of storage layers (#28, data storage pattern) and the plurality of conductive layers (#50, conductive layer), and a plurality of second blocking layers (#48, dielectric layers) disposed between the first blocking layer (#26) and the plurality of conductive layers (#50).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Yang in view of Izumi with the teaching of Lee in order to improve retention characteristics of data stored in the data storage patterns according to Lee, [0119].
Regarding Claim 10, Yang in view of Izumi teaches the memory device as described in claim 9.
Yang in view of Izumi does not teach a thickness of the first blocking layer is greater than a thickness of the corresponding second blocking layer.
However, Lee teaches a thickness of the first blocking layer is greater than a thickness of the corresponding second blocking layer ([0065], Figures 5A-E, thickness of layer #26 is greater than of layer #48).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Yang in view of Izumi with the teaching of Lee for reason set forth in rejection of claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20210351196A1 – Figure 2a
US20130270643A1 – Figures 6, 7A-D
US20230051815A1 – Figures 10H-11
US20190198509A1 – Figure 16
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/TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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