DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the election filed July 14, 2026.
Election/Restrictions
Applicant’s election without traverse of claims 1-17 and 21-23 in the reply filed on July 14, 2026 is acknowledged.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” “embodiments of the present disclosure provide” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE HAVING NANOSTRUCTURE TRANSISTOR.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the plurality of semiconductor layers" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claims 11-17 are rejected as being dependent upon rejected claim 10.
In regard to claim 21, it is not understood how the plurality of first semiconductor channel layers are vertically stacked over the first device region and the plurality of second semiconductor channel layers are vertically stacked over the second device region; when the plurality of first semiconductor channel layers are actually vertically stacked in the first device region and the plurality of second semiconductor channel layers are vertically stacked in the second device region. Interpreted as in the first and second device regions.
Claims 22-23 are rejected as being dependent upon rejected claim 21.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2021/0320035 A1).
In regard to claim 1, Xie et al. teach a semiconductor device structure (Figure 14), comprising: a source/drain feature 216 disposed over a substrate 202; a plurality of semiconductor layers 206 vertically stacked over the substrate 202 and in contact with the source/drain feature 216; a gate electrode layer 904 surrounding a portion of each of the plurality of the semiconductor layers 206; a first dielectric spacer 210 in contact with a first side of a topmost semiconductor layer 206 of the plurality of semiconductor layers 206; and a second dielectric spacer 210 in contact with a second side of the topmost semiconductor layer 206 of the plurality of semiconductor layers 206 (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 2, Xie et al. teach the first and second dielectric spacers 210 are in contact with a gate spacer 218 (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 3, Xie et al. teach the plurality of semiconductor layers 206 formed of germanium (See page 3, paragraph [0038]) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 4, Xie et al. teach each of the semiconductor layers 206 formed of a strained germanium (See page 3, paragraph [0038]) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 7, Xie et al. teach the topmost semiconductor layer 206 of the plurality of semiconductor layers 206 having a first thickness (in YY), and the first dielectric spacer 210 having a second thickness (in YY) that is greater than the first thickness (in YY) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 8, Xie et al. teach an etch stop layer 204 disposed between a bottommost semiconductor layer 206 of the plurality of semiconductor layers 206 and the substrate 202, wherein the etch stop layer 204 has a first concentration of germanium (See page 3, paragraph [0038]) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 9, Xie et al. teach each of the plurality of semiconductor layers 206 having a second concentration of germanium that is greater than the first concentration of germanium (See page 3, paragraph [0038]) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
As best understood and in regard to claim 10, Xie et al. teach semiconductor device structure (Figure 14), comprising: a plurality of first semiconductor layers 206 (in XX) disposed at a first device region XX of a substrate 202; a first source/drain feature 216 in contact with each of the plurality of first semiconductor layers 206 (in XX); a first dielectric spacer 210 contacting a first side of a topmost first semiconductor layer 206 (in XX) of the plurality of semiconductor layers 206; a plurality of second semiconductor layers 206 (in YY) disposed at a second device region YY of the substrate 202; and a second source/drain feature 216 (in YY) in contact with each of the plurality semiconductor layers 206 (in YY), wherein the number of the plurality of first semiconductor layers 206 (in XX) and the number of the plurality of second semiconductor layers 206 (in YY) are different (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 11, Xie et al. teach the first source/drain feature 216 (in XX) having a first height and the second source/drain feature 216 (in YY) having a second height different than the first height (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 12, Xie et al. teach the plurality of first semiconductor layers 206 (in XX) comprising strained germanium and the plurality of second semiconductor layers 206 (in YY) comprising silicon (See page 3, paragraph [0038]).
In regard to claim 13, Xie et al. teach an etch stop layer 204 disposed between a bottommost first semiconductor layer 206 (in XX) of the plurality of first semiconductor layers 206 (in XX) and the substrate 202, wherein the etch stop layer 204 has a concentration of germanium less than a concentration of germanium of the first semiconductor layers 206 (in XX) (See page 3, paragraph [0038]) (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 14, Xie et al. teach a second dielectric spacer 210 contacting the first source/drain feature 216 and a second side of the topmost first semiconductor layer 206 of the plurality of semiconductor layers 206 (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 15, Xie et al. teach the first dielectric spacer 210 further in contact with a first gate spacer 218 (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
In regard to claim 16, Xie et al. teach a topmost second semiconductor layer 206 of the plurality of second semiconductor layers 206 having a first side in contact with a second gate spacer 222 (Figure 14, pages 2-4, paragraphs [0025]-[0053]).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6 is objected to as being dependent upon objected claim 5.
As best understood, claim 17 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
As best understood, claims 21-23 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The following patents are cited to further show the state of the art with respect to semiconductor device structures:
Basker et al. (US 2019/0189769 A1) Liaw (US 2022/0157941 A1)
Xie et al. (US 2021/0320035 A1) You et al. (US 2023/0335645 A1)
Zang et al. (US 9,847,391 B1) Zang et al. (US 10,103,238 B1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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IMS
August 25, 2026
/IDA M SOWARD/Primary Examiner, Art Unit 2898
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