Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1,4,5,7,11, 12, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Min ( US-20220223526-A1; Min) in view of Song et al. (US-20190097048-A1; Song).
Regarding claim 1, Min disclose a semiconductor device comprising: an active pattern (Fig. 32, AP1; ¶218,225) that comprises a lower pattern (Fig. 32, BP1; ¶218,225) extending in a first direction (X) on a substrate (Fig. 32, 100; ¶52) and a sheet pattern (Fig. 32, UP1; ¶218,225) on the lower pattern; a field insulating layer (Fig. 34, 105; ¶223) that defines the active pattern on the substrate; a gate structure (Fig. 32, GS; ¶52) on the lower pattern and comprising a gate insulating layer (Fig. 32, 130; ¶223) and a gate electrode (Fig. 32, 120; ¶224), the gate electrode extending in a second direction (Z) perpendicular to the first direction; a gate spacer (Fig. 32, 140; ¶225) …; and a source/drain pattern (Fig. 32, 150; ¶80) on the lower pattern and in contact with the sheet pattern.
Min is silent on a gate spacer at least partially surrounding the gate structure and comprising a first portion on a sidewall of the gate structure and a second portion on a bottom surface of the gate structure.
Song discloses a semiconductor device comprising a nanosheet (not shown; ¶19), wherein a gate spacer structure (Fig. 2, 121/142; ¶23, 34) at least partially surrounding the gate structure (Fig. 2, 122-125; ¶23, 34) and comprising a first portion (Fig. 2, 142; ¶23, 34) on a sidewall of the gate structure and a second portion (Fig. 2, 121; ¶23, 34) on a bottom surface of the gate structure.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a spacer on the bottom surface of the gate to form an interface between the nanosheet and the gate structure.
Regarding claim 4, Min in view of Song disclose the semiconductor device of claim 1, wherein the second portion (Fig. 2, 121; ¶23, 34 Song) of the gate spacer (Fig. 2, 121/142; ¶23, 34 Song) is between the field insulating layer (Fig. 3, 105; ¶23 Song) and the gate structure. (Fig. 2, 122-125; ¶23, 34 Song)
The vertical portion of the second portion is between a portion of the gate and the field oxide.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a spacer on the bottom surface of the gate to form an interface between the nanosheet and the gate structure.
Regarding claim 5, Min in view of Song disclose the semiconductor device of claim 1, wherein the second portion (Fig. 3, 121; ¶23, 34 Song) of the gate spacer (Fig. 3, 121/142; ¶23, 34 Song) is on a sidewall of the lower pattern. (Fig. 3, 20; ¶26 Song)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a spacer on the bottom surface of the gate to form an interface between the nanosheet and the gate structure.
Regarding claim 7, Min in view of Song disclose the semiconductor device of claim 1, further comprising a first interlayer insulating layer (Fig. 2, 191; ¶115 Min) on the field insulating layer (Fig. 34, 105; ¶223 Min) and the source/drain pattern (Fig. 32, 150; ¶80 Min), wherein a lower portion of the first interlayer insulating layer overlaps (when combined) the second portion of the gate spacer (Fig. 2, 121; ¶23, 34 Song) in the first direction.(x)
The interlayer would overlap the second portion of the gate spacer due to its position under the gate structure.
Regarding claim 11, Min in view of Song disclose the semiconductor device of claim 1, wherein the gate structure (Fig. 32, GS; ¶52 Min) comprises a gate capping pattern (Fig. 32, 145; ¶23, 56 Min) on a top surface of the gate electrode.
Regarding claim 12, Min in view of Song disclose the semiconductor device of claim 1, wherein the sheet pattern (Fig. 32, UP1; ¶218,225 Min) comprises a plurality of sheet patterns spaced apart from each other, wherein the gate structure comprises an inner gate structure (Fig. 32, 120; ¶224 Min) between the lower pattern (Fig. 32, BP1; ¶225 Min) and the sheet pattern and between ones of the plurality of sheet patterns that are adjacent to each other, wherein the inner gate structure comprises the gate electrode and the gate insulating layer (Fig. 32, 130; ¶223 Min), and wherein the semiconductor device further comprises an inner spacer (Fig. 32, 142; ¶225 Min) between the inner gate structure and the source/drain pattern. (Fig. 32, 150; ¶222 Min)
Regarding claim 20, Min discloses a semiconductor device comprising: an active pattern (Fig. 32, AP1; ¶218,225) that comprises a lower pattern (Fig. 32, BP1; ¶218,225) extending in a first direction (x) on a substrate (Fig. 32, 100; ¶52) and a sheet pattern (Fig. 32, UP1; ¶218,225) on the lower pattern; a field insulating layer (Fig. 34, 105; ¶223) that defines the active pattern on the substrate; a gate structure (Fig. 32, 120/130; ¶218,223-224) on the lower pattern and comprising a gate insulating layer (Fig. 32, 130; ¶218,223) and a gate electrode (Fig. 32, 120; ¶218,223-224), the gate electrode extending in a second direction (Z) perpendicular to the first direction; a gate spacer (Fig. 32, 141; ¶218,225) …; a source/drain pattern (Fig. 32, 150; ¶218,222) on the lower pattern and in contact with the sheet pattern; and a first interlayer insulating layer (Fig. 32/34, 191; ¶218,225) on the field insulating layer and the source/drain pattern and extending in the second direction,
Min is silent on a gate spacer at least partially surrounding the gate structure and comprising a first portion on a sidewall of the gate structure and a second portion on a bottom surface of the gate structure… wherein the second portion of the gate spacer is between the field insulating layer and the gate structure, and is not between the field insulating layer and the first interlayer insulating layer.
Song discloses a semiconductor device comprising a gate spacer (Fig. 3/3, 121/142; ¶23, 34 Song) at least partially surrounding the gate structure and comprising a first portion on a sidewall of the gate structure and a second portion (Fig. 2/3, 121; ¶23, 34 Song) on a bottom surface of the gate structure (Fig. 2/3, 122-125; ¶23, 34 Song)… wherein the second portion of the gate spacer is between (Fig. 3, the vertical portion) the field insulating layer (Fig. 2/3, 105; ¶23, 34 Song) and the gate structure (Fig. 2/3, 122-125; ¶23, 34 Song), and is not between the field insulating layer and the first interlayer insulating layer. (Fig. 2/3, 160; ¶23, 34 Song)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form a spacer on the bottom surface of the gate to form an interface between the nanosheet and the gate structure.
Allowable Subject Matter
Claims 2,3,6,8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The most relevant art cited above in combination discloses a semiconductor device comprising a nanosheet, gate structure, field insulating layer, source/drain regions, and interlayer insulation layers. However the art is silent on the claimed configurations cited below in combination with the rest of the claimed limitations.
Regarding claim 2, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the gate spacer comprises a first insulating layer in contact with the gate structure and a second insulating layer at least partially surrounding the first insulating layer”, as recited in Claim 2, with the remaining features.
Regarding claim 3 the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the gate spacer further comprises a third insulating layer between the second insulating layer and the field insulating layer, and wherein the first insulating layer and the third insulating layer comprise a same material.”, as recited in Claim 3, with the remaining features.
Regarding claim 6, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the second portion of the gate spacer is free of overlap with the sheet pattern in a third direction perpendicular to the second direction.”, as recited in Claim 6, with the remaining features.
Regarding claim 8, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " wherein the second portion of the gate spacer is not between the first interlayer insulating layer and the field insulating layer.”, as recited in Claim 8, with the remaining features.
Regarding claim 9, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " the field insulating layer is on a first portion of a sidewall of the lower pattern, and the second portion of the gate spacer is on a second portion of the sidewall of the lower pattern, and wherein the first and second portions of the sidewall of the lower pattern are connected to each other.”, as recited in Claim 9, with the remaining features.
Regarding claim 10, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " t further comprising a liner layer on a top surface of the substrate and a sidewall of the lower pattern, wherein the field insulating layer is on the liner layer.”, as recited in Claim 10, with the remaining features.
Claims 13-19 allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The most relevant art cited above in combination discloses a semiconductor device comprising a nanosheet, gate structure, field insulating layer, source/drain regions, and interlayer insulation layers. However the art is silent on the claimed configurations cited below in combination with the rest of the claimed limitations.
Regarding claim 13, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a second portion that extends in the first direction along a top surface of the field insulating layer;”, as recited in Claim 13, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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