Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
"Semiconductor Device with Insulated Stacked External Terminals"
Because the claims are directed to a semiconductor device in which external terminals are arranged in a stacked relationship and separated by one or more insulating members, with the terminals being exposed on different surfaces of a sealing resin. This terminal configuration appears to be a key structural aspect of the invention and distinguishes the claimed device from conventional semiconductor packages.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 3 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Specifically, the limitation:
"a third external terminal electrically connected to the semiconductor chip and having a part laterally opposed parallel to the second external terminal"
renders the claim indefinite because the phrase "laterally opposed parallel" lacks clarity and fails to provide objective boundaries for the claimed spatial relationship between the third external terminal and the second external terminal.
While the term "parallel" generally denotes structures extending in substantially the same direction, the meaning of "laterally opposed" is unclear. The claim does not define whether "laterally opposed" requires the terminals to be side-by-side, horizontally facing one another, laterally offset from one another, disposed on opposite sides of an intervening structure, or otherwise arranged. Furthermore, neither the claim language nor the specification provides sufficient guidance for determining when two terminals satisfy the recited "laterally opposed parallel" relationship.
As a result, one of ordinary skill in the art would not be reasonably apprised of the metes and bounds of the claimed invention and would be unable to determine with reasonable certainty the scope of claim 3.
For purposes of examination, the examiner interprets the phrase "laterally opposed parallel" to mean that a portion of the third external terminal is arranged laterally adjacent to and extends substantially parallel to a portion of the second external terminal. However, this interpretation is adopted solely for examination purposes and should not be construed as an indication that the claim language is definite.
Applicant is invited to amend the claim to more clearly recite the intended positional relationship between the terminals using definite structural terminology supported by the specification. For example, Applicant may specify that the terminals are "laterally adjacent," "horizontally opposed," "disposed on opposite lateral sides of," or otherwise define the relative arrangement with objective boundaries.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6 and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu (US 2018/0166377).
Regarding claim 1, Liu discloses a semiconductor device 300 (Fig. 3) comprising:
(Note: Fig. 3 is primarily relied upon because it illustrates the claimed stacked-terminal arrangement. Fig. 1 is additionally referenced for identification of corresponding reference-numbered elements and details not expressly labeled in Fig. 3. The identically numbered elements in Figs. 1 and 3 to refer to the same structures).
an insulated circuit substrate, namely substrate 104 having conductive layers separated by a ceramic insulating layer (Fig. 1; Fig. 3; [0016]);
a semiconductor chip provided on a top surface side of the insulated circuit substrate, namely silicon dies 106A and 106B shown in Fig. 1 and represented as the silicon dies ("Si") mounted on substrate 104 in Fig. 3 ([0016]);
a sealing resin provided so as to seal the semiconductor chip, namely housing 308, which encloses at least part of the semiconductor device, wherein the housing is formed by an overmolding process that encapsulates the device into an enclosed structure (Fig. 3; [0024]);
a first external terminal electrically connected to the semiconductor chip so as to be exposed on a first side surface of the sealing resin, namely terminal structure 302A/304A electrically connected to the silicon dies and exposed to the outside through opening 306 in housing 308 (Fig. 3; [0024]);
a second external terminal electrically connected to the semiconductor chip and having a part opposed parallel to the first external terminal on an upper side of the first external terminal so as to be exposed on a top surface of the sealing resin, namely terminal structure 302B/304B electrically connected to the silicon dies, disposed above terminal structure 302A/304A in a stacked and parallel relationship, and exposed to the outside through opening 310 in housing 308 (Fig. 3; [0024]); and
a first insulating member interposed between the first external terminal and the second external terminal, namely electric insulator 118 provided between the stacked planar terminals 302A and 302B (Fig. 3; [0020]).
As shown in Fig. 3, terminal structure 302B/304B is arranged on an upper side of terminal structure 302A/304A, with electric insulator 118 interposed therebetween. The opposing portions of terminal structures 302A/304A and 302B/304B extend in substantially parallel planes, thereby meeting the limitation that the second external terminal has a part opposed parallel to the first external terminal on an upper side of the first external terminal.
Regarding claim 6, Liu discloses the semiconductor device of claim 1. Fig. 3 shows second external terminal structure 302B/304B exposed through opening 310 in housing 308. As shown in Fig. 3, the exposed upper surface of busbar 304B is substantially coplanar with the adjacent stepped top surface portion of housing 308 surrounding opening 310. Although housing 308 includes stepped top surface regions, the exposed top surface of busbar 304B lies in the same plane as the adjacent top surface portion of housing 308, thereby sharing a common plane with a top surface of the sealing resin.
Accordingly, Liu teaches that the top surface of the second external terminal exposed on the top surface of the sealing resin has a plane common to the top surface of the sealing resin.
Regarding claim 9, Liu discloses the semiconductor device of claim 1. Fig. 3 discloses second external terminal structure 302B/304B disposed above first external terminal structure 302A/304A in a stacked configuration within housing 308. As shown in Fig. 3, planar terminals 302A and 302B are arranged in opposed and substantially parallel relationship, with insulating member 118 interposed therebetween. The opposed parallel portions of terminals 302A and 302B are located within housing 308 prior to being exposed through openings 306 and 310.
Accordingly, Liu teaches that the second external terminal is opposed parallel to the first external terminal on an inside of the sealing resin.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20180166377) in view of Hatano (US 20210398881).
Regarding claim 2, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
a third external terminal electrically connected to the semiconductor chip and having a part opposed parallel to the first external terminal on a lower side of the first external terminal so as to be exposed on the first side surface of the sealing resin; and a second insulating member interposed between the first external terminal and the third external terminal.
However, Fig. 9 of Hatano discloses a third external terminal 41 electrically connected to semiconductor chips 22A and 22B ([0041]) and having a part opposed parallel to first external terminal 42 on a lower side of first external terminal 42, wherein terminals 41 and 42 are exposed on the same side surface of sealing resin 7 (Fig. 9; [0041]). Hatano further teaches a second insulating member 49, namely an insulation plate, interposed between first external terminal 42 and third external terminal 41 (Fig. 9; [0040]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the lower stacked terminal structure of Hatano into the semiconductor device of Liu because Hatano teaches that insulation plate 49 permits adjacent external terminals 41 and 42 to be arranged in a vertically stacked configuration while maintaining electrical isolation. Applying Hatano's known stacked-terminal arrangement to Liu would have yielded the predictable result of providing an additional external connection while maintaining insulation between adjacent terminals and increasing terminal density without increasing package size.
Regarding claim 3, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
a third external terminal electrically connected to the semiconductor chip and having a part laterally opposed parallel to the second external terminal so as to be exposed on the first side surface of the sealing resin.
(For purposes of examination, the examiner interprets the phrase "laterally opposed parallel" to mean that a portion of the third external terminal is arranged laterally adjacent to and extends substantially parallel to a portion of the second external terminal).
However, Fig 9 of Hatano discloses a third external terminal 41 electrically connected to semiconductor chips 22A and 22B ([0041]) and exposed on a side surface of sealing resin 7. Hatano further discloses an upper terminal 43 that extends substantially parallel to terminal 41, with terminals 41 and 43 being arranged on opposite sides of terminal 42 and exposed on the same side surface of sealing resin 7 (Fig. 9; [0040]-[0041]). Accordingly, terminal 41 constitutes the claimed third external terminal having a part laterally opposed parallel to the second external terminal under the examiner's interpretation.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the additional terminal arrangement taught by Hatano into the semiconductor device of Liu because Hatano teaches a compact multi-terminal stacked configuration that provides additional external electrical connections while maintaining electrical isolation and efficient package utilization. Applying Hatano's terminal arrangement to Liu would have yielded the predictable result of increasing terminal density and connection flexibility without increasing package size.
Regarding claim 4, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
a third external terminal electrically connected to the semiconductor chip so as to be exposed on a second side surface of the sealing resin opposed to the first side surface.
However, Fig 9 pf Hatano discloses a third external terminal 43 electrically connected to semiconductor chips 22A and 22B and exposed on a side surface of sealing resin 7 opposite the side surface on which terminals 41 and 42 are exposed (Fig. 9; [0041]). Accordingly, Hatano teaches a third external terminal exposed on a second side surface of the sealing resin opposed to the first side surface.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the external terminal arrangement taught by Hatano into the semiconductor device of Liu because Hatano teaches providing external terminals on opposing side surfaces of a resin-sealed semiconductor package, thereby increasing routing flexibility and enabling additional electrical connections without significantly increasing package size. Applying Hatano's known terminal arrangement to Liu would have yielded the predictable result of providing an additional external terminal on an opposite side surface of the package while maintaining the functionality of the semiconductor device.
Regarding claim 5, Liu discloses the semiconductor device of claim 1. But Liu and the claim 2 modification do not expressly teach:
a fourth external terminal electrically connected to the semiconductor chip so as to be exposed on a second side surface of the sealing resin opposed to the first side surface.
However, Fig 9 of Hatano discloses external terminal 43 electrically connected to semiconductor chips 22A and 22B and exposed on a side surface of sealing resin 7 opposite the side surface on which terminals 41 and 42 are exposed (Fig. 9; [0041]). Accordingly, terminal 43 teaches the claimed fourth external terminal exposed on a second side surface of the sealing resin opposed to the first side surface.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the additional external terminal arrangement taught by Hatano into the semiconductor device of Liu because Hatano teaches providing external terminals on opposing side surfaces of a resin-sealed semiconductor package, thereby increasing routing flexibility and enabling additional electrical connections while maintaining a compact package structure. Applying Hatano's known terminal arrangement to Liu would have yielded the predictable result of providing an additional external terminal on an opposite side surface of the package while preserving the electrical functionality of the semiconductor device.
Regarding claim 10, Liu discloses the semiconductor device of claim 1. But Liu and the claim 2 modification do not expressly teach:
wherein the third external terminal is opposed parallel to the first external terminal from an inside to an outside of the sealing resin.
However, Fig 9 of Hatano discloses third external terminal 41 and first external terminal 42 arranged in an opposed and substantially parallel relationship with insulation plate 49 interposed therebetween. As shown in Fig. 9, terminals 41 and 42 maintain the opposed parallel relationship from within sealing resin 7 to the side surface of sealing resin 7 where the terminals are exposed (Fig. 9; [0040]-[0041]). Accordingly, Hatano teaches that the third external terminal is opposed parallel to the first external terminal from an inside to an outside of the sealing resin.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the terminal arrangement taught by Hatano into the semiconductor device of Liu because Hatano teaches a stacked and insulated terminal structure that extends from the interior of a resin-sealed package to the exterior connection region while maintaining electrical isolation between adjacent terminals. Applying Hatano's known arrangement to Liu would have yielded the predictable result of providing an additional external electrical connection while preserving insulation and efficient package utilization.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20180166377) in view of Muto (US 20190378785).
Regarding claim 7, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
wherein a top surface of the second external terminal exposed on the top surface of the sealing resin is recessed downward from the top surface of the sealing resin.
However, Fig 3 of Muto discloses a top electrode 30 ([0088]) exposed through opening 32 on the top surface of sealing resin 70 ([0110]). As shown in Fig. 3, the exposed top surface of top electrode 30 is positioned below the surrounding top surface of sealing resin 70, thereby being recessed downward from the top surface of the sealing resin.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Liu such that the exposed second external terminal is recessed below the surrounding top surface of the sealing resin as taught by Muto. Muto teaches that the electrode remains externally accessible while being recessed within the sealing resin. Applying Muto's recessed terminal arrangement to Liu would have yielded the predictable result of protecting the exposed terminal surface from mechanical damage and external contact while maintaining electrical accessibility for connection.
Regarding claim 8, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
wherein a top surface of the second external terminal exposed on the top surface of the sealing resin projects upward from the top surface of the sealing resin.
However, Fig 40 of Muto discloses upper electrode 30 ([0097]) exposed through opening 32 in sealing resin 70. As shown in Fig. 40, the top surface 31 of upper electrode 30 is positioned above top surface 76 of sealing resin 70 ([0151]), such that upper electrode 30 projects upward from the surrounding top surface of the sealing resin.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Liu such that the exposed second external terminal projects upward from the surrounding top surface of the sealing resin as taught by Muto. Muto teaches that the electrode remains externally accessible while protruding above the sealing resin surface. Applying Muto's protruding terminal arrangement to Liu would have yielded the predictable result of increasing the exposed contact area and facilitating external electrical connection while maintaining the resin-sealed package structure.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 20180166377) in view of Mori (US 20240282677).
Regarding claim 11, Liu discloses the semiconductor device of claim 1. But Liu does not expressly teach:
wherein a thickness of a part of the second external terminal exposed on the top surface of the sealing resin is greater than a thickness of a part of the second external terminal not exposed on the top surface of the sealing resin.
However, Fig 9 of Mori discloses second external terminal 111, wherein exposed portion 1112 extends above and is exposed on the top surface of sealing resin 40 ([0033], [0035]), while portion 1114 is embedded within sealing resin 40 and is not exposed on the top surface of the sealing resin ([0037]). As shown in Fig. 10, the thickness of exposed portion 1112 is greater than the thickness of embedded portion 1114.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the second external terminal of Liu to have the thickness profile taught by Mori because Mori teaches increasing the thickness of the exposed terminal portion while maintaining a thinner embedded portion. Applying Mori's terminal structure to Liu would have yielded the predictable result of providing a larger exposed connection region while maintaining efficient internal terminal routing within the resin-sealed package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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