DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species I directed to Fig. 1-3 (claims 1-10) in the reply filed on June 12th, 2026 is acknowledged. The traversal is on the ground(s) that Fig. 6 should be included within Species I. The Examiner would not disagree with the Applicant’s remarks; However, the Examiner did not include Fig. 6 in Species I because Fig. 6 can be generic embodiment that can be applied to all Species. Also, The Examiner did not specifically group Fig. 6 to one single Species nor being mutually exclusive to any of Species I-VI.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by GARDNER et al. (Pub. No.: US 2023/0335555 A1), hereinafter as GARDNER.
Regarding claim 1, GARDNER discloses a semiconductor device in Fig. 1A-1B comprising: a substrate (substrate 10) (see Fig. 1A and [0037]); a vertical channel (vertical channel 12U in stack 15-2) having a tube shape extending from the substrate in a first direction (vertical direction in Fig. 1A) perpendicular to a surface of the substrate (see Figs. 1A-1B and [0039]); an outer insulating layer (gate structure 18U only include gate dielectric in stack 15-2) on an outer circumferential surface of the vertical channel (see Fig. 1A and [0045]); a gate electrode (gate electrode 24U in stack 15-2) facing the vertical channel with the outer insulating layer between the gate electrode and the vertical channel (see Fig. 1A and [0045]); an inner insulating layer (core dielectric 38 in stack 15-) on an inner circumferential surface of the vertical channel (see Figs. 1A-1B and [0043]); and a conductive layer (back gate 40 in stack 15-2) in the vertical channel and facing the vertical channel with the inner insulating layer between the conductive layer and the vertical channel (see Fig. 1A-1B and [0040], [0044]).
Regarding claim 2, GARDNER discloses the semiconductor device of claim 1, wherein the gate electrode surrounds an outer circumference of the vertical channel (gate electrode 24U has right and left portion surrounding channel 12U) (see Fig. 1A).
Regarding claim 3, GARDNER discloses the semiconductor device of claim 1,
wherein the conductive layer faces the gate electrode (see Fig. 1A).
Regarding claim 4, GARDNER discloses the semiconductor device of claim 1, further comprising: a source electrode (S/D region 14U and/or S/D interconnects 20U) and a drain electrode (S/D regions16U and/or S/D interconnects 22U), wherein the source electrode and the drain electrode are each electrically connected to the vertical channel and apart from each other in the first direction (see Fig. 1A and [0039]).
Regarding claim 5, GARDNER discloses the semiconductor device of claim 4, wherein the gate electrode is between the source electrode and the drain electrode (see Fig. 1A).
Regarding claim 6, GARDNER discloses the semiconductor device of claim 1, wherein the vertical channel includes a transition metal dichalcogenide (TMD) material (vertical channel 12U comprising WS2) (see [0041]).
Regarding claim 7, GARDNER discloses semiconductor device of claim 6, wherein the TMD material includes at least one of MoS2, MoSe-2, MoTe--2, and HfS2 (see [0041]).
Regarding claim 8, GARDNER discloses semiconductor device of claim 1, wherein the vertical channel includes polysilicon (vertical channel 12U comprising Si in polycrystalline form) (see [0041]).
Regarding claim 9, GARDNER discloses semiconductor device of claim 1, further comprising: a source electrode (S/D region 14U and/or S/D interconnects 20U) and a drain electrode (S/D regions16U and/or S/D interconnects 22U) electrically connected to the vertical channel (see Fig. 1A and [0039]); and a vertical channel transistor array (stacks 15-1 and 15-2) including a plurality of vertical channel transistor structures (plurality of vertical NMOS/PMOS in stacks 15-1 and 15-2), wherein the plurality of vertical channel transistor structures are arranged in a two-dimensional (2D) manner on a plane (defined by a surface of substrate 10) perpendicular to the first direction, and at least one vertical channel transistor structure among the plurality of vertical channel transistor structures includes the vertical channel, the outer insulating layer, the gate electrode, the inner insulating layer, the conductive layer, and the source electrode and the drain electrode electrically connected to the vertical channel (vertical transistors ins stacks 15-1 and 15-2 including vertical NMOS or PMOS having elements 12U, 18U, 24U, 38, 40, 14U/20U and 16U/22U) (see Fig. 1A-1B and [0037-0038], [0041]).
Regarding claim 10, GARDNER discloses semiconductor device of claim 9, wherein the vertical channel transistor array includes a plurality of vertical channel transistor arrays (vertical transistors 5U stacked on vertical transistors 5L) stacked in the first direction with an isolation layer (dielectric 34 and dielectric 36) therebetween (see Fig. 1A and [0040]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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