Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed April 23, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 8, 15
b. Pending: 1-20
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "1400" and "1412" have both been used to designate “FAST PLANE (NORMAL)” in Figs. 14A and 14B. The curve 1412 should instead be labeled “FAST PLANE (FAKE)” because Fig. 14B is an illustration of the “FAKE FAST PLANE CASE,” based on the drawing title. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
In the “Description of the Enabling Embodiment” section of the Specification, in para. [0096] on p.28, make the following change:
“In multi-plane programming, a memory structure is divided into multiple planes and memory cells in multiple planes connected to the same word lines may be programmed concurrently”
In para. [00107] on p.32, make the following change:
“In response to a determination that one or more planes failed (i.e., did not reach memory state B), an IBS judgment mode is triggered”
In para. [00107] on p.32, make the following change:
“In one example, the high state judgment may be performed subsequent to a programming loop in which one or more planes reached the memory state G (e.g., subsequent to a 10th programming loop) as shown in FIG. 12B at 1208”
Appropriate correction is required.
Claim Objections
Claims 1 and 15 are objected to because of the following informalities:
Regarding claim 1, make the following change:
“the control circuitry is configured to detect a neighbor plane disturb (NPD) defect during the multi-plane programming operation by:”
Regarding claim 15, make the following change:
“the control means detects a neighbor plane disturb (NPD) defect during the multi-plane programming operation by:”
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Examiner notes that claims 15, 16, 19, and 20 refer to a “control means”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 7 and 14 recite the limitation "the first program verify voltage" in the second line of claim 7 on page 2 and in the second line of claim 14 on page 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6, 8, 12-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Puthenthermadam et al. (US Pub. 20190214100 A1; “PS”).
Regarding independent claim 1, PS discloses a memory device (Fig. 1: memory device 100; [0057]), comprising:
a plurality of memory cells arranged in a plurality of planes ([0057]: The memory structure 126 may comprise multiple planes, such as neighbor planes P0 and P1. Each plane may include one or more blocks of memory cells. For example, P0 includes blocks B0a-B0d and P1 includes blocks B1a-B1d); and
control circuitry (control circuitry 110; [0060]) configured to perform a multi-plane programming operation in which memory cells in each of the plurality of planes are programmed in a single programming operation ([0050]: Concurrent program operations can be performed in which blocks in different planes, one block per plane, are subject to the same program and verify signals), wherein, to perform the multi-plane programming operation, the control circuitry is configured to detect a neighbor plane disturb (NPD) defect during the multi-plane programming operation ([0050]: a defect in one of the blocks can affect the programming in another block. For instance, a weak short circuit may develop between a selected word line and an adjacent unselected word line in a defective block; [0051]: Techniques provided herein address the above and other issues. In one approach, a bad block is quickly detected and removed from further programming during concurrent multi-block program operations, to minimize the threshold voltage upshift in the remaining one or more good blocks) by
performing a bit scan operation to identify, based on a first program verify threshold, a fast plane and a slow plane from among the plurality of planes ([0165]: FIG. 11F depicts the Vth distribution 1103 of FIG. 10A, showing fastest-programming memory cells and slowest-programming memory cells in a good block after PL3…The Vth distribution represents a set of memory cells which are subject to the A-state verify test. This can include the memory cells assigned to the A-state and/or other higher states. A line 1103b represents a midpoint of the Vth distribution 1103 such that a portion 1103c of the Vth distribution represents slowest-programming memory cells among the memory cells which are subject to the verify test and the portion 1103d of the Vth distribution represents fastest-programming memory cells among the memory cells which are subject to the verify test. As mentioned, by detecting the fastest-programming memory cells in a good block, a comparison of programming speed with another block can be initiated sooner in the program operation; [0158]: A-state verify test, e.g., a first verify test; [0172]: step 1311 indicates that a program milestone is reached by a fast block (e.g., a fast-programming block) before one or more slow blocks (e.g., a slow-programming block)…The milestone can involve a predetermined number of memory cells passing a verify test, for example. Examiner asserts that Vva may be the first verify threshold, and that the identification of fast and slow memory cells and fast and slow blocks can also be applied to fast and slow planes, since multiple blocks make up a plane, per Fig. 8A),
determining whether the fast plane passes a second program verify threshold greater than the first program verify threshold (in reference to Fig. 13D, per [0178]: at decision step 1333, if a predetermined number of fastest-programming memory cells in the second block pass the first verify test…a second verify test is passed by a predetermined number of fastest-programming memory cells in the first block. These are the fastest-programming memory cells among the memory cells in the first block which are subject to the second verify test; [0179]: The first verify test can be a verify test of a first assigned programmed data state which uses a first verify voltage, and the second verify test can be a verify test of a second assigned programmed data state which uses a second verify voltage, higher than the first verify voltage. See previous explanation of applying procedures related to fast and slow cells to the plane level),
identifying one of the fast plane and the slow plane as a failed plane based on the determination of whether the fast plane passes the second program verify threshold ([0180]: If at decision step 1335, a predetermined number of fastest-programming memory cells in the second block pass the second verify test…the program operation continues for the first and second blocks at step 1337…If decision step 1335 is false, step 1336 terminates the program operation for the second block and continues the program operation for the first block), and
terminating programming of the identified failed plane (Fig. 13D: step 1336; Fig. 13B: step 1317).
Regarding claim 5, PS discloses the limitations of claim 1. Further, through PS:
wherein, to perform the bit scan operation, the control circuitry is configured to determine respective portions of voltage distributions of the memory cells of each of the plurality of planes that are greater than the first program verify threshold ([0158]: When a predetermined number of memory cells in a first block pass the A-state verify test, e.g., a first verify test, this can trigger a process for comparing the program speed of the first block to the program speed of a second block. This comparison can involve determining whether the second block passes the first verify test within a specified number, e.g., three, of additional program loops. Examiner asserts that a bit scan may be analogous to a verify operation, and concludes that a number of memory cells passing a verify test is analogous to portions of memory cell distributions).
Regarding claim 6, PS discloses the limitations of claim 5. Further, through PS:
wherein, to determine whether the fast plane passes the second program verify threshold, the control circuitry is configured to determine a portion of a voltage distribution of the memory cells of the fast plane that is greater than the second program verify threshold ([0180]: If at decision step 1335, a predetermined number of fastest-programming memory cells in the second block pass the second verify test. Examiner asserts that a number of the fastest-programming memory cells in the second block is analogous to a portion of memory cells in a fast plane).
Independent claim 8 is nearly identical in claimed subject matter as claim 1
except for being drafted in method format instead of device format and is rejected for
the same reasons as independent claim 1.
Regarding claim 12, PS discloses all the limitations of claim 8. Claim 12
recites substantially the same limitations as claim 5, and henceforth is rejected for the same reasons.
Regarding claim 13, PS discloses all the limitations of claim 12. Claim 13 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Independent claim 15 is nearly identical in claimed subject matter as claim 1
except for using the word “means” instead of the phrase “circuitry configured to” and is rejected for the same reasons as independent claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 9-11, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over PS (US Pub. 20190214100 A1) as applied to claims 1, 8, and 15 above, and further in view of Tian et al. (US Pub. 20220415421 A1; “Tian”).
Regarding claim 2, PS discloses the limitations of claim 1, and further
through PS:
wherein the control circuitry (Fig. 1: 110) is configured to (i) identify the fast plane as the failed plane in response to a determination that the fast plane passes the second program verify threshold ([0180]) and
a determination that the fast plane does not pass the second program verify threshold ([0178]-[0179]).
PS does not explicitly disclose:
(ii) identify the slow plane as the failed plane in response to a determination that the fast plane does not pass the second program verify threshold.
However, Tian teaches:
(ii) identify the slow plane as the failed plane in response to a determination that the fast plane does not pass the second program verify threshold ([0159]: the Controller Device determines a difference between a number of program loops required to complete programming for a particular programmed state (e.g., programmed state S1 or other programmed state) for the two planes. If the determined difference exceeds a predetermined amount (e.g., 4 loops), the Controller Device determines that an EPT status failure has occurred and that a defect exists on the slower plane. Examiner asserts that per [00116]-[00117] of the Specification and Figs. 14 of the present application, a normal faster plane will not pass the second program verify threshold when it completes programming. So, since the determination of slower plane failure depends on program loops required to complete programming for the two planes, the determination also depends on the faster plane not passing the second program verify voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Tian to PS wherein the control circuitry is configured to identify the slow plane as the failed plane in response to a determination that the fast plane does not pass the second program verify threshold in order to reduce program disturb on other planes by terminating programming on a disturbed plane (Tian, [0032]).
Regarding claim 3, PS and Tian together disclose the limitations of claim 2, and further through PS:
wherein identifying the fast plane includes determining, based on the first program verify threshold, whether the fast plane has reached a judgment memory state ([0051]: A difference in program speeds between the blocks can be quickly detected by detecting when the fastest-programming memory cells in each block pass a verify test, such as a verify test of a lowest programmed data state; [0172]: step 1311 indicates that a program milestone is reached by a fast block (e.g., a fast-programming block) before one or more slow blocks (e.g., a slow-programming block). Examiner asserts that the “verify test of a lowest programmed data state” and the “first verify test” are analogous to the first program verify threshold).
Regarding claim 4, PS and Tian together disclose the limitations of claim 3, and further through PS:
wherein the second program verify threshold corresponds to a memory state higher than the judgment memory state ([0195]: The program loop margin is the number of program loops which are used to determine if a slower programming block is defective, after a faster programming block reaches a programming milestone such as passing a first verify test; [0179]: The first verify test can be a verify test of a first assigned programmed data state which uses a first verify voltage, and the second verify test can be a verify test of a second assigned programmed data state which uses a second verify voltage, higher than the first verify voltage. Examiner concludes that passing a first verify test may be the same as a milestone, and these are analogous to reaching a judgment memory state. So, the state corresponding to passing the second verify test is higher than a milestone or judgment memory state).
Regarding claim 9, PS discloses all the limitations of claim 8. Claim 9 recites substantially the same limitations as claim 2, and henceforth is rejected for the same reasons.
Regarding claim 10, PS and Tian together disclose all the limitations of claim 9. Claim 10 recites substantially the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 11, PS and Tian together disclose all the limitations of claim 10. Claim 11 recites substantially the same limitations as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 16, PS discloses all the limitations of claim 15. Claim 16 recites substantially the same limitations as claim 2, and henceforth is rejected for the same reasons.
Regarding claim 17, PS and Tian together disclose all the limitations of claim 16. Claim 17 recites substantially the same limitations as claim 3, and henceforth is rejected for the same reasons.
Regarding claim 18, PS and Tian together disclose all the limitations of claim 17. Claim 18 recites substantially the same limitations as claim 4, and henceforth is rejected for the same reasons.
Regarding claim 19, PS and Tian together disclose all the limitations of claim 18. Claim 19 recites substantially the same limitations as claim 5, and henceforth is rejected for the same reasons.
Regarding claim 20, PS and Tian together disclose all the limitations of claim 19. Claim 20 recites substantially the same limitations as claim 6, and henceforth is rejected for the same reasons.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over PS (US Pub. 20190214100 A1) as applied to claims 1 and 8, and further in view of Kim (US Pub. 20100172185 A1).
Regarding claim 7, PS discloses the limitations of claim 1. PS discloses a first and second program verify thresholds, but does not disclose:
wherein the second program verify threshold is offset from the first program verify voltage by approximately 1 V.
However, Kim teaches:
wherein the second program verify threshold is offset from the first program verify voltage by approximately 1 V (per claim 7: the second program verify voltage ranges from the first program verify voltage minus 1.0 V to the first program verify voltage plus 1.0 V).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Kim to modified PS wherein the second program verify threshold is offset from the first program verify voltage by approximately 1 V in order to prevent data loss by raising the threshold voltage of a memory cell (Kim, [0024]).
Regarding claim 14, PS and Kim together disclose all the limitations of claim 8. Claim 14 recites substantially the same limitations as claim 7, and henceforth is rejected for the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chin et al. (US Pub. 20220399061 A1): [0010], [0087], and [0089] are relevant to claim 1.
Guo (US Pub. 20230148416 A1): [0002], [0019], [0021], and [0024] are relevant to claim 1.
Tian et al. (US Pub. 20250226044 A1): [0029], [0114], [0116], and [0127] are relevant to claim 1.
Zainuddin et al. (US Pub. 20250372185 A1): [0004] and [0171]-[0175] are relevant to claim 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIZABETH ROSE AGGER whose telephone number is (571)270-0250. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rich Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
/E.R.A./Examiner, Art Unit 2824
12/26/2025