CTNF 18/643,149 CTNF 91738 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 4/23/2024, 11/25/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3-13 are rejected under 35 U.S.C. 112(b) In claim 3, lines 8, the limitation of “the plurality of upper and lower contact vias” renders the claim indefinite because it lacks antecedent basis and no contact via was previously recited. Therefore, it is suggested Applicant change “the plurality of upper and lower contact vias” in claim 3, line 8 to “a plurality of upper and lower contact vias”. For examination purposes, the limitation will be interpreted and examined as “a plurality of upper and lower contact vias”. Correction is requested. Claims 4-13 are also rejected as being dependent on claim 3. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 3, 5, 9 and 14-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee (US 2023/0292508) . Regarding claim 1, Lee discloses, in at least figures 4-5D and related text, a semiconductor device, comprising: an active pattern (AP, [41]) extending in a first direction (D2, figures), on a substrate (100, [41]); first (CH1, [42]) to fourth (CH4, [42]) channel structures stacked in order on one region of the active pattern (AP, [41]), said first (CH1, [42]) to fourth (CH4, [42]) channel structures including respective first (SP1/SP2/SP3, [44]) to fourth (SP10/SP11/SP12, [55]) semiconductor patterns, which are stacked and spaced apart from each other in a vertical direction (D3, figures) perpendicular to an upper surface of the substrate (100, [41]); a first gate structure (GE1/GE2, [57]) that crosses the one region of the active pattern (AP, [41]), extends in a second direction (D1, figures) intersecting the first direction (D2, figures), and surrounds the first (SP1/SP2/SP3, [44]) and second (SP4/SP5/SP6, [50]) semiconductor patterns; a second gate structure (GE3/GE4, [57]) that extends on the first gate structure (GE1/GE2, [57]), in the second direction (D1, figures), and surrounds the third (SP7/SP8/SP9, [53]) and fourth (SP10/SP11/SP12, [55]) semiconductor patterns; a pair of first source/drain patterns (SD1, [45]) connected to corresponding ends of the first semiconductor pattern (SP1/SP2/SP3, [44]), on opposing sides of the first gate structure (GE1/GE2, [57]); a pair of second source/drain patterns (SD2, [48]) connected to corresponding ends of the second semiconductor pattern (SP4/SP5/SP6, [50]), on opposing sides of the first gate structure (GE1/GE2, [57]); a pair of third source/drain patterns (SD3, [53]) connected to corresponding ends of the third semiconductor pattern (SP7/SP8/SP9, [53]), on opposing sides of the second gate structure (GE3/GE4, [57]); a pair of fourth source/drain patterns (SD4, [55]) connected to corresponding ends of the fourth semiconductor pattern (SP10/SP11/SP12, [55]), on opposing sides of the second gate structure (GE3/GE4, [57]); an interlayer insulating layer (CSS, [47]) covering a plurality of the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns; and a plurality of upper wiring lines (CTL1 to CTL6, [56]) including at least one upper wiring line (CTL1/CTL2/CTL5/CTL6, [95]-[99]) electrically coupled through the interlayer insulating layer (CSS, [47]) to at least one of the first (SD1, [45]) through fourth (SD4, [55]) source/drain patterns. Regarding claim 3, Lee discloses the semiconductor device of claim 1 as described above. Lee further discloses, in at least figures 4-5D and related text, first contact structures (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) extending in the second direction (D1, figures) from each of the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns disposed on one side of the first (GE1/GE2, [57]) and second (GE3/GE4, [57]) gate structures, and second contact structures (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) extending in the second direction (D1, figures) from each of the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns disposed on the other side of the first (GE1/GE2, [57]) and second (GE3/GE4, [57]) gate structures; and wherein each of the first (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) and second (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) contact structures is connected to at least one of the plurality of upper (VEP1 to VEP3 of AC1 to AC3 and ND, [71], [74], [79], [85]) and lower contact vias. Regarding claim 5, Lee discloses the semiconductor device of claim 3 as described above. Lee further discloses, in at least figures 4-5D and related text, at least one of the first (HEP1 to HEP4 of AC1 to AC4 in left side of GES, [71], [74], [79], [84], figures) and second (HEP1 to HEP4 of AC1 to AC4 in right side of GES, [71], [74], [79], [84], figures) contact structures has an extended length different from extended lengths of the other contact structures (figures). Regarding claim 9, Lee discloses the semiconductor device of claim 3 as described above. Lee further discloses, in at least figures 4-5D and related text, the first (SD1, [46]) and third (SD3, [53]) source/drain patterns include a first conductivity-type semiconductor, and the second (SD2, [51]) and fourth (SD4, [55]) source/drain patterns include a second conductivity-type semiconductor. Regarding claim 14, Lee discloses the semiconductor device of claim 1 as described above. Lee further discloses, in at least figures 4-5D and related text, an inter-gate insulating layer (DMP, [47]) disposed between the first gate structure (GE1/GE2, [57]) and the second gate structure (GE3/GE4, [57]). Regarding claim 15, Lee discloses the semiconductor device of claim 14 as described above. Lee further discloses, in at least figures 4-5D and related text, a first intermediate insulating pattern (DMP, [47]) disposed between the first channel structure (CH1, [42]) and the second channel structure (CH2, [42]); and a second intermediate insulating pattern (DMP, [47]) disposed between the third channel structure (CH3, [42]) and the fourth channel structure (CH4, [42]). Regarding claim 16, Lee discloses the semiconductor device of claim 1 as described above. Lee further discloses, in at least figures 4-5D and related text, the first semiconductor pattern (SP1/SP2/SP3, [44]) is arranged to at least partially overlap the second semiconductor pattern (SP4/SP5/SP6, [50]) in the vertical direction on the cross-sectional surface in the second direction (D1, figures) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2, 21-22 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2023/0292508) in view of Kim (US 2023/0095830) . Regarding claim 2, Lee discloses the semiconductor device of claim 1 as described above. Lee further discloses, in at least figures 4-5D and related text, a plurality of upper contact vias (VEP1 to VEP3 of AC1 to AC3 and ND, [71], [74], [79], [85]) electrically connecting each of the plurality of upper wiring lines (CTL1/CL2/CL5/CTL6, [56]) to at least one of the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns. Lee does not explicitly disclose a plurality of lower wiring lines disposed on a lower surface of the substrate; a plurality of lower contact vias penetrating through the substrate and electrically connecting each of the plurality of lower wiring lines to at least one of the first to fourth source/drain patterns; wherein the plurality of lower wiring lines includes a first power line and a second power line; wherein the plurality of lower contact via includes: a first power transfer via electrically connecting the first power line to at least one of first to fourth source/drain patterns disposed on one side of the first and second gate structures; a second power transfer via electrically connecting the second power line to at least one of first to fourth source/drain patterns disposed on the other side of the first and second gate structures. Kim teaches, in at least figures 3, 4B, 4C, and related text, the device comprising a plurality of lower wiring lines (LMI1, [81]) disposed on a lower surface of the substrate (100, [80]); a plurality of lower contact vias (TVI, [82]) penetrating through the substrate (100, [80]) and electrically connecting each of the plurality of lower wiring lines (LMI1, [81]) to at least one of the first to fourth source/drain patterns (SD1/SD2, [48]); wherein the plurality of lower wiring lines (LMI1, [81]) includes a first power line (POR1, [79]) and a second power line (POR2, [79]); wherein the plurality of lower contact via (LVI1/LVI2, [90], [91]) includes: a first power transfer via (LVI2, [91]) electrically connecting the first power line (POR1, [79]) to at least one of first to fourth source/drain patterns (SD2, [48]) disposed on one side of the first (GE of AR1, [88], figures) and second (GE of AR2, [88], figures) gate structures; a second power transfer via (LVI1, [90]) electrically connecting the second power line (POR2, [79]) to at least one of first to fourth source/drain patterns (SD1, [48]) disposed on the other side of the first (GE of AR1, [88], figures) and second (GE of AR2, [88], figures) gate structures, for the purpose of providing three-dimensional semiconductor devices with increased integration ([4]). Lee and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Kim because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lee to have the plurality of lower wiring lines disposed on a lower surface of the substrate; the plurality of lower contact vias penetrating through the substrate and electrically connecting each of the plurality of lower wiring lines to at least one of the first to fourth source/drain patterns; the plurality of lower wiring lines including a first power line and a second power line; the plurality of lower contact via including: a first power transfer via electrically connecting the first power line to at least one of first to fourth source/drain patterns disposed on one side of the first and second gate structures; a second power transfer via electrically connecting the second power line to at least one of first to fourth source/drain patterns disposed on the other side of the first and second gate structures, as taught by Kim, for the purpose of providing three-dimensional semiconductor devices with increased integration ([4], Kim). Regarding claim 21, Lee discloses, in at least figures 4-5D and related text, a semiconductor device, comprising: an active pattern (AP, [41]) disposed on a substrate (100, [41]); a first channel structure (CH1, [42]) including a plurality of first semiconductor patterns (SP1/SP2/SP3, [44]) stacked and spaced apart from each other on one region of the active pattern (AP, [41]); a second channel structure (CH2, [42]) including a plurality of second semiconductor patterns (SP4/SP5/SP6, [50]) stacked and spaced apart from each other on the first channel structure (CH1, [42]); a third channel structure (CH3, [42]) including a plurality of third semiconductor patterns (SP7/SP8/SP9, [53]) stacked and spaced apart from each other on the second channel structure (CH2, [42]); a fourth channel structure (CH4, [42]) including a plurality of fourth semiconductor patterns (SP10/SP11/SP12, [55]) stacked and spaced apart from each other on the third channel structure (CH3, [42]); a gate structure (GE1/GE2/GE3/GE4, [57]) crossing the one region of the active pattern (AP, [41]) and surrounding the plurality of first (SP1/SP2/SP3, [44]) to fourth (SP10/SP11/SP12, [55]) semiconductor patterns; a pair of first source/drain patterns (SD1, [45]) connected to both ends of the plurality of first semiconductor patterns (SP1/SP2/SP3, [44]), respectively, on both sides of the gate structure (GE1/GE2/GE3/GE4, [57]); a pair of second source/drain patterns (SD2, [48]) disposed on the pair of first source/drain patterns (SD1, [45]) and connected to both ends of the plurality of second semiconductor patterns (SP4/SP5/SP6, [50]), respectively; a pair of third source/drain patterns (SD3, [53]) disposed on the pair of second source/drain patterns (SD2, [48]) and connected to both ends of the plurality of third semiconductor patterns (SP7/SP8/SP9, [53]), respectively; a pair of fourth source/drain patterns (SD4, [55]) disposed on the pair of third source/drain patterns (SD3, [53]) and connected to both ends of the plurality of fourth semiconductor patterns (SP10/SP11/SP12, [55]), respectively; first contact structures (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) connected to the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns disposed on one side of both sides of the gate structure (GE1/GE2/GE3/GE4, [57]), respectively; second contact structures (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) connected to the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns disposed on the other side on both sides of the gate structure (GE1/GE2/GE3/GE4, [57]), respectively. Lee does not explicitly disclose a first power line and a second power line disposed on a lower surface of the substrate; a first power transfer via penetrating through the substrate and electrically connecting the first power line to at least one of the first contact structures; a second power transfer via penetrating through the substrate and electrically connecting the second power line to at least one of the second contact structures. Kim teaches, in at least figures 3, 4B, 4C, and related text, the device comprising a first power line (LMI1 for POR1, [79], [81]) and a second power line (LMI1 for POR2, [79], [81]) disposed on a lower surface of the substrate (100, [80]); a first power transfer via (TVI/LVI2, [82], [91]) penetrating through the substrate (100, [80]) and electrically connecting the first power line (LMI1 for POR1, [79], [81]) to at least one of the first contact structures (AC2, [49]); a second power transfer via (TVI/LVI1, [82], [90]) penetrating through the substrate (100, [80]) and electrically connecting the second power line (LMI1 for POR2, [79], [81]) to at least one of the second contact structures (AC1, [49]), for the purpose of providing three-dimensional semiconductor devices with increased integration ([4]). Lee and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Kim because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lee to have the first power line and a second power line disposed on a lower surface of the substrate; the first power transfer via penetrating through the substrate and electrically connecting the first power line to at least one of the first contact structures; the second power transfer via penetrating through the substrate and electrically connecting the second power line to at least one of the second contact structures, as taught by Kim, for the purpose of providing three-dimensional semiconductor devices with increased integration ([4], Kim). Regarding claim 22, Lee in view of Kim discloses the semiconductor device of claim 21 as described above. Lee further discloses, in at least figures 4-5D and related text, an interlayer insulating layer (CSS, [47]) covering the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns; a plurality of first wiring lines (CTL1 to CTL6, [56]) disposed on the interlayer insulating layer (CSS, [47]); and a plurality of first contact vias (VEP1 to VEP3 of AC1 to AC3 and ND, [71], [74], [79], [85]) connecting each of the plurality of first wiring lines (CTL1 to CTL6, [56]) to at least one of the first (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) and second (HEP1 to HEP4 of AC1 to AC4, [71], [74], [79], [84]) contact structures. Regarding claim 26, Lee discloses, in at least figures 4-5D and related text, a semiconductor device, comprising: an active pattern (AP, [41]) extending on a substrate (100, [41]) in a first direction (D2, figures); a first channel structure (CH1, [42]) including a plurality of first semiconductor patterns (SP1/SP2/SP3, [44]) stacked and spaced apart from each other on one region of the active pattern (AP, [41]) in a vertical direction perpendicular to an upper surface of the substrate (100, [41]); a second channel structure (CH2, [42]) including a plurality of second semiconductor patterns (SP4/SP5/SP6, [50]) stacked and spaced apart from each other in the vertical direction on the first channel structure (CH1, [42]); a third channel structure (CH3, [42]) including a plurality of third semiconductor patterns (SP7/SP8/SP9, [53]) stacked and spaced apart from each other in the vertical direction on the second channel structure (CH2, [42]); a fourth channel structure (CH4, [42]) including a plurality of fourth semiconductor patterns (SP10/SP11/SP12, [55]) stacked and spaced apart from each other in the vertical direction on the third channel structure (CH3, [42]); a first intermediate insulating pattern (DMP, [47]) disposed between the first channel structure (CH1, [42]) and the second channel structure (CH2, [42]); a second intermediate insulating pattern (DMP, [47]) disposed between the third channel structure (CH3, [42]) and the fourth channel structure (CH4, [42]); a first gate structure (GE1/GE2, [57]) crossing the one region of the active pattern (AP, [41]), extending in a second direction (D1, figures) intersecting the first direction (D2, figures) and surrounding the plurality of first semiconductor patterns (SP1/SP2/SP3, [44]) and the plurality of second semiconductor patterns (SP4/SP5/SP6, [50]); a second gate structure (GE3/GE4, [57]) extending on the first gate structure (GE1/GE2, [57]) in the second direction (D1, figures) and surrounding the plurality of third semiconductor patterns (SP7/SP8/SP9, [53]) and the plurality of fourth semiconductor patterns (SP10/SP11/SP12, [55]); an inter-gate insulating layer (DMP, [47]) disposed between the first gate structure (GE1/GE2, [57]) and the second gate structure (GE3/GE4, [57]); a pair of first source/drain patterns (SD1, [45]) disposed on the active pattern (AP, [41]) on both sides of the first gate structure (GE1/GE2, [57]) and connected to both ends of the plurality of first semiconductor patterns (SP1/SP2/SP3, [44]), respectively; a pair of second source/drain patterns (SD2, [48]) connected to both ends of the plurality of second semiconductor patterns (SP4/SP5/SP6, [50]), respectively, on both sides of the first gate structure (GE1/GE2, [57]); a pair of third source/drain patterns (SD3, [53]) connected to both ends of the plurality of third semiconductor patterns (SP7/SP8/SP9, [53]), respectively, on both sides of the second gate structure (GE3/GE4, [57]); a pair of fourth source/drain patterns (SD4, [55]) connected to both ends of the plurality of fourth semiconductor patterns (SP10/SP11/SP12, [55]), respectively, on both sides of the second gate structure (GE3/GE4, [57]); an interlayer insulating layer (CSS, [47]) covering the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns; a plurality of first wiring lines (CTL1 to CTL6, [56]) disposed on the interlayer insulating layer (CSS, [47]); a plurality of first contact vias (VEP1 to VEP3 of AC1 to AC3, [71], [74], [79], [85]) connecting each of the plurality of first wiring lines (CTL1 to CTL6, [56]) to at least one of the first (SD1, [45]) to fourth (SD4, [55]) source/drain patterns through the interlayer insulating layer (CSS, [47]). Lee does not explicitly disclose a plurality of second wiring lines disposed on a lower surface of the substrate; a plurality of second contact vias connecting each of the plurality of second wiring lines to at least one of the first to fourth source/drain patterns through the substrate. Kim teaches, in at least figures 3, 4B, 4C, and related text, the device comprising a plurality of second wiring lines (LMI1, [79]) disposed on a lower surface of the substrate (100, [80]); a plurality of second contact vias (TVI/LVI1/LVI2, [82], [90], [91]) connecting each of the plurality of second wiring lines (LMI1, [79]) to at least one of the first to fourth source/drain patterns (SD1/SD2, [48]) through the substrate (100, [80]), for the purpose of providing three-dimensional semiconductor devices with increased integration ([4]). Lee and Kim are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Kim because they are from the same field of endeavor. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Lee to have the plurality of second wiring lines disposed on a lower surface of the substrate; the plurality of second contact vias connecting each of the plurality of second wiring lines to at least one of the first to fourth source/drain patterns through the substrate, as taught by Kim, for the purpose of providing three-dimensional semiconductor devices with increased integration ([4], Kim) . Allowable Subject Matter Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, and 4 that recite "at least one of the first contact structures extends in a direction opposite to the other first contact structure, and at least one of the second contact structures extends in a direction opposite to the other second contact structure" in combination with other elements of the base claims 1, 3, and 4. Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, and 6 that recite "the plurality of upper contact vias include an upper contact via connected to two or more of the first contact structures or two or more of the second contact structures" in combination with other elements of the base claims 1, 3, and 6. Claim 7 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, and 7 that recite "the plurality of lower contact vias includes a lower contact via connected to two or more of the first contact structures or two or more of the second contact structures" in combination with other elements of the base claims 1, 3, and 7. Claim 8 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, and 8 that recite "an interconnecting via connecting two or more of the first contact structures to each other or two or more of the second contact structures to each other in the interlayer insulating layer" in combination with other elements of the base claims 1, 3, and 8. Claims 10-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, 9, and 10 that recite "the plurality of upper wiring lines includes first to third upper wiring lines extending in the first direction; the first to third upper wiring lines are sequentially arranged in the first direction, and the active pattern is positioned between the second and third upper wiring lines in view of a plane" in combination with other elements of the base claims 1, 3, 9, and 10. Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 21, 22, and 23 that recite "the plurality of first contact vias include first contact vias connected to two or more of the first contact structures or two or more of the second contact structures" in combination with other elements of the base claims 21, 22, and 23. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TONG-HO KIM/Primary Examiner, Art Unit 2811 Application/Control Number: 18/643,149 Page 2 Art Unit: 2811 Application/Control Number: 18/643,149 Page 3 Art Unit: 2811 Application/Control Number: 18/643,149 Page 4 Art Unit: 2811 Application/Control Number: 18/643,149 Page 5 Art Unit: 2811 Application/Control Number: 18/643,149 Page 6 Art Unit: 2811 Application/Control Number: 18/643,149 Page 7 Art Unit: 2811 Application/Control Number: 18/643,149 Page 8 Art Unit: 2811 Application/Control Number: 18/643,149 Page 9 Art Unit: 2811 Application/Control Number: 18/643,149 Page 10 Art Unit: 2811 Application/Control Number: 18/643,149 Page 11 Art Unit: 2811 Application/Control Number: 18/643,149 Page 12 Art Unit: 2811 Application/Control Number: 18/643,149 Page 13 Art Unit: 2811 Application/Control Number: 18/643,149 Page 14 Art Unit: 2811 Application/Control Number: 18/643,149 Page 15 Art Unit: 2811 Application/Control Number: 18/643,149 Page 16 Art Unit: 2811 Application/Control Number: 18/643,149 Page 17 Art Unit: 2811 Application/Control Number: 18/643,149 Page 18 Art Unit: 2811 Application/Control Number: 18/643,149 Page 19 Art Unit: 2811
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