Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/23/2024 is being considered by the examiner.
Claim Objections
Claim 4 is objected to because of the following informalities:
second instance of "first dielectric material layer" limitation missing an article. Understood as "the first dielectric material layer" following antecedent basis requirement for examination purposes. Appropriate correction is required.
Claim 15 is objected to because of the following informalities:
The limitation "the ovonic threshold switch material" missing preposition prior to. Understood as "adhesion of the ovonic threshold switch material" for examination purposes. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (US 11631716 B2) in view of Hashemi et al. (US 20200251652 A1).
Regarding claim 1, Wan et al. (US 11631716 B2) teaches a method of forming a magnetoresistive memory array (cross-point spin-transfer torque MRAM array), comprising:
forming a stack structure (“layer stack”) including a one-dimensional array of first conductive lines (electrically conductive lines 30) laterally extending along a first horizontal direction (hd1), an array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140) each comprising a reference layer (132), a tunnel barrier layer (134), and a free layer (136) located over (FIG.2) the first conductive lines;
forming a dielectric matrix layer (dielectric matrix 160);
forming selector elements (selector 150); and
forming a one-dimensional array of second conductive lines (second electrically conductive line 90) laterally extending along a second horizontal direction (hd2) over (FIG.11A) the selector elements.
Wan et al. (US 11631716 B2), however, does not teach comprising:
a two-dimensional array of sacrificial pillar structures located over the array of magnetic tunnel junction stacks;
forming a dielectric matrix layer laterally surrounding the two-dimensional array of sacrificial pillar structures;
forming a two-dimensional array of via cavities by removing the two-dimensional array of sacrificial pillar structures selective to the dielectric matrix layer; and
forming selector elements at least within volumes of the two-dimensional array of via cavities;
Hashemi et al. teaches comprising:
a two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P, use with underlying bottom electrodes 16) located over (FIG.2) the array of magnetic tunnel junction stacks (MTJ pillar 18P);
forming a dielectric matrix layer (dielectric material layer 32L) laterally surrounding (FIG.4) the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P);
forming a two-dimensional array of via cavities (top electrode cavity 34) by removing (FIG.6) the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P) selective to ([0050]) the dielectric matrix layer (dielectric material layer 32L); and
forming selector elements (top electrode 38) at least within volumes (FIG.7) of the two-dimensional array of via cavities (top electrode cavity 34);
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 2, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) teaches the dielectric matrix layer (dielectric matrix 160) but does not teach wherein:
the dielectric matrix layer is formed by depositing a dielectric fill material around and over the two-dimensional array of sacrificial pillar structures, and by performing a planarization process that removes portions of the deposited dielectric fill material from above a horizontal plane including top surfaces of the two-dimensional array of sacrificial pillar structures; and a top surface of the dielectric matrix layer comprises a planar surface after performing the planarization process.
Hashemi et al., however, teaches wherein:
the dielectric matrix layer (dielectric material layer 32L) is formed by depositing a dielectric fill material (passivation material liner 30L) around and over (FIG.4) the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P), and by performing a planarization process (chemical mechanical polishing (CMP)) that removes (FIG.5) portions of the deposited dielectric fill material from above a horizontal plane including top surfaces ([0047]) of the two-dimensional array of sacrificial pillar structures; and
a top surface (FIG.5, topmost surface) of the dielectric matrix layer (dielectric material portion 32) comprises a planar surface ([0048], coplanar with 28P) after performing the planarization process.
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 3, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) does not teach wherein the two-dimensional array of sacrificial pillar structures comprises diamond-like carbon sacrificial pillar structures.
However, Hashemi et al. teaches wherein the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P) comprises diamond-like carbon (amorphous carbon) sacrificial pillar structures.
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 4, as best understood based on the claim objection identified above, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) teaches wherein:
the one-dimensional array of first conductive lines (electrically conductive lines 30) are located within a first dielectric material layer (FIG.8 and [0070], first rail structures 100); and
the array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140) is formed by depositing and patterning a layer stack (FIG.2 and [0053], formed as a stack of continuous layers) including a continuous reference layer (132L), a continuous tunnel barrier layer (continuous nonmagnetic tunnel barrier layer 134L), and a continuous free layer (continuous free magnetization material layer 136L) over (FIG.3) the one-dimensional array of first conductive lines and over (FIG.8) the first dielectric material layer.
Wan et al. (US 11631716 B2), however, does not teach the two-dimensional array of sacrificial pillar structures is formed over the layer stack by depositing and patterning a sacrificial pillar material layer.
Hashemi et al. teaches the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P) is formed over (FIG.2) the layer stack (MTJ pillar 18P) by depositing and patterning ([0040]) a sacrificial pillar material layer (sacrificial material layer 28).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 5, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 4. Wan et al. (US 11631716 B2) teaches further comprising:
forming a two-dimensional array of etch mask portions ([0064], discrete masking material portions 177) over the sacrificial pillar material layer (continuous electrically conductive material layer 170L); and
performing an anisotropic etch process ([0064]) that transfers a pattern ([0064]) in the two-dimensional array of etch mask portions through the sacrificial pillar material layer (continuous electrically conductive material layer 170L), wherein remaining patterned portions ([0065]) of the sacrificial pillar material layer comprise the two-dimensional array of sacrificial pillar structures (pillar structures 300).
However, Wan et al. (US 11631716 B2) does not teach sacrificial pillar material layer and sacrificial pillar structures. Hashemi et al. teaches sacrificial pillar material layer (sacrificial material layer 28) and two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 6, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 4. Wan et al. (US 11631716 B2) teaches wherein the layer stack (FIG.2, comprising layer 170L) is patterned by performing an etch process ([0064], anisotropic etch process) that etches unmasked portions ([0064]) of the layer stack employing the two-dimensional array of sacrificial pillar structures (top of pillar structures 300: discrete masking material portions 177).
However, Wan et al. does not teach employing the two-dimensional array of sacrificial pillar structures as an etch mask.
Hashemi et al. teaches employing the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P) as an etch mask ([0050], inherent with selective etching process).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 7, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) teaches further comprising:
forming a first metallic material layer (continuous metallic seed layer 110L) and a layer stack (FIG.3) including a continuous reference layer (continuous synthetic antiferromagnetic (SAF) layer stack 120L), a continuous tunnel barrier layer (continuous nonmagnetic tunnel barrier layer 134L), and a continuous free layer (continuous free magnetization material layer 136L) over the substrate (8);
forming a one-dimensional array of etch mask portions (line-shaped masking material portions 187) over (FIG.8) the layer stack; and
transferring a pattern ([0070]) of the one-dimensional array of etch mask portions through the layer stack and the first metallic material layer, wherein patterned portions ([0070], each first electrically conductive line 30) of the layer stack comprise the array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140), and patterned portions ([0070], each metallic seed layer 110) of the first metallic material layer comprises the one-dimensional array of first conductive lines (electrically conductive lines 30).
Regarding claim 9, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 7. Wan et al. (US 11631716 B2) teaches further comprising forming insulating rails (in-process dielectric rail structures 380) between neighboring pairs (FIG.17) of magnetic tunnel junction stacks (FIG.18, magnetic tunnel junction (MTJ) 140 comprising layers 134) within the array (FIG.18) of magnetic tunnel junction stacks.
Regarding claim 10, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 9. Wan et al. (US 11631716 B2) does not teach wherein the two-dimensional array of sacrificial pillar structures (pillar structures 300) is formed over the insulating rails (in-process dielectric rail structures 380).
Therefore, an alternative embodiment within Wan et al. (US 11631716 B2) is used to supply the limitation of insulating rails, so to teach wherein the two-dimensional array of sacrificial pillar structures (pillar structures 300) is formed over (FIG.11A) the insulating rails (first rail structures 100, instead) and the array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140 comprising layers 134) by depositing and patterning ([0080]) a sacrificial pillar material layer (continuous electrically conductive material layer 170L).
Wan et al. (US 11631716 B2), however, still does not teach the two-dimensional array of sacrificial pillar structures and a sacrificial pillar material layer. Hashemi et al. teaches the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P) and a sacrificial pillar material layer (sacrificial material layer 28).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have provided Hashemi et al.’s sacrificial material and dielectric fill technique for forming openings above MTJ structures to Wan et al.’s cross-point MRAM array to provide self-aligned via cavities, in which selector material is deposited, rather than being etched into final pillar form. That way, selector sidewalls can be formed without etching it, thereby reducing sidewall damage and further improving performance, reliability, and yield.
Regarding claim 11, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 10. Wan et al. (US 11631716 B2) teaches further comprising vertically recessing portions ([0093] and FIG.19, first dielectric rail structure 382) of the insulating rails (in-process dielectric rail structure 380) and etching the array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140) that are not masked ([0063], anisotropic etch terminating at layer 134L) by the two-dimensional array of sacrificial pillar structures (pillar structures 300), wherein top surfaces of the insulating rails are vertically recessed (FIG.19) at least to a horizontal plane including bottom surfaces of the free layers (136) within the array of magnetic tunnel junction stacks, and wherein remaining portions of the free layers comprise a two-dimensional array of free layers (continuous nonmagnetic tunnel barrier layer 134L).
Regarding claim 12, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 11. Wan et al. (US 11631716 B2) teaches wherein a bottom surface of the dielectric matrix layer (dielectric fill material layer 160) is formed on the recessed top surfaces ([0093] and FIG.19, first dielectric rail structure 382) of the insulating rails (in-process dielectric rail structure 380) and on horizontal surfaces (FIGS.8 and 19) of the tunnel barrier layers (134) within the array of magnetic tunnel junction stacks (magnetic tunnel junction (MTJ) 140).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (US 11631716 B2) in view of Hashemi et al. (US 20200251652 A1) and Kim et al. (US 20170069832 A1).
Regarding claim 8, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 7. Wan et al. (US 11631716 B2) teaches further comprising:
forming an electrically conductive metal, metal nitride or carbon nitride lower electrode layer (continuous electrically conductive material layer 170L) over the layer stack (FIG.6), wherein the one-dimensional array of etch mask portions (line-shaped masking material portions 187) is formed over (FIG.7) the lower electrode layer, and the pattern of the one-dimensional array of etch mask portions is transferred ([0084]) through the lower electrode layer to pattern the lower electrode layer into lower electrodes (FIG.15, in-process rail structures 311); and
the pattern ([0070]) of the one-dimensional array of etch mask portions is transferred through the layer stack ([0070]) and the first metallic material layer by performing an etch process (anisotropic etch process).
However, Wan et al. (US 11631716 B2) does not teach performing an etch process that employs the lower electrodes as an etch mask structure.
Kim et al. teaches performing an etch process ([0054]) that employs the lower electrodes (upper electrode 126b of mask structure 128a) as an etch mask structure ([0054]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have employed Kim et al.’s technique of using electrode over MTJ structure as etch mask to Wan et al.’s cross-point MRAM fabrication process to pattern MTJ structure, thereby simplifying pattern transfer process while maintaining Wan et al.’s cross-point MRAM structure.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (US 11631716 B2) in view of Hashemi et al. (US 20200251652 A1) and Hou et al. (CN 114766061 A).
Regarding claim 13, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) does not teach further comprising: forming an array of lower electrodes over the array of magnetic tunnel junction stacks, wherein top surfaces of the lower electrodes are exposed upon removal of the two-dimensional array of sacrificial pillar structures; and forming a layer of nucleation inhibitor molecules on physically exposed surfaces of the dielectric matrix layer while suppressing adhesion of the nucleation inhibitor molecules on the top surfaces of the lower electrodes.
However, Hashemi et al. teaches forming ([0019]) an array of lower electrodes (bottom electrode 16) over the array of magnetic tunnel junction stacks (MTJ stack 18), wherein top surfaces (MTJ cap layer 26P) of the lower electrodes are exposed (FIG.6) upon removal of the two-dimensional array of sacrificial pillar structures (patterned sacrificial material 28P).
And Hou et al. teaches forming (FIG.3) a layer of nucleation inhibitor molecules (first nucleation suppression layer 992) on physically exposed surfaces of the dielectric matrix layer (first bonding dielectric layer 970) while suppressing adhesion ([0034]) of the nucleation inhibitor molecules on the top surfaces of the lower electrodes (first metal bond pads 988).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Hou et al.’s selective deposition and nucleation techniques to cross-point MRAM structure and process of Wan et al., as modified by Hashemi et al., to selectively form material on exposed conductive regions while suppressing deposition on surrounding dielectric regions. This technique, as taught by Hou et al., of providing nucleation inhibition later on dielectric surfaces while leaving electrode surfaces exposed for selective deposition, allows formation of selector material only where needed, avoiding dielectric nucleation and suppresses unwanted or unnecessary selector growth on dielectric surfaces, thereby improving performance, reliability, and yield.
Regarding claim 14, Wan et al. (US 11631716 B2) in view of Hashemi et al. and Hou et al. (CN 114766061 A). teaches the method of claim 13. Wan et al. (US 11631716 B2) teaches selector elements (selectors 150) but does not teach wherein at least a portion of the selector elements is formed by performing a selective deposition process that deposits a selector material of the selector elements on the top surfaces of the lower electrodes while suppressing nucleation of the selector material over the layer of nucleation inhibitor molecules.
However, Hou et al. teaches wherein at least a portion of the selector elements ([0036], second metal) is formed by performing a selective deposition process (atomic layer deposition (ALD) process) that deposits a selector material (self-assembly material (SAM) precursor) of the selector elements on the top surfaces of the lower electrodes (first metal bonding pad 988) while suppressing nucleation ([0036]) of the selector material over the layer of nucleation inhibitor molecules (first nucleation suppression layer 992).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Hou et al.’s selective deposition and nucleation techniques to cross-point MRAM structure and process of Wan et al., as modified by Hashemi et al., to selectively form material on exposed conductive regions while suppressing deposition on surrounding dielectric regions. This technique, as taught by Hou et al., of providing nucleation inhibition later on dielectric surfaces while leaving electrode surfaces exposed for selective deposition, allows formation of selector material only where needed, avoiding dielectric nucleation and suppresses unwanted or unnecessary selector growth on dielectric surfaces, thereby improving performance, reliability, and yield.
Regarding claim 15, as best understood based on the claim objection identified above, Wan et al. (US 11631716 B2) in view of Hashemi et al. and Hou et al. (CN 114766061 A). teaches the method of claim 14. Wan et al. (US 11631716 B2) teaches monolayer of ovonic threshold switch material ([0050]) but does not teach wherein the selective deposition process further comprises a precursor adhesion step in which at least one monolayer of ovonic threshold switch material is adsorbed to the top surfaces of the lower electrodes while adhesion the ovonic threshold switch material on the layer of nucleation inhibitor molecules is suppressed.
However, Hou et al. teaches wherein the selective deposition process (atomic layer deposition (ALD) process) further comprises a precursor adhesion step in which at least one monolayer of ovonic threshold switch material (self-assembled monolayer (SAM): metal-organic precursor gas molecules) is adsorbed ([0037]) to the top surfaces of the lower electrodes (first metal bonding pad 988) while adhesion of the ovonic threshold switch material on the layer of nucleation inhibitor molecules (first nucleation inhibiting layer 992) is suppressed ([0037]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Hou et al.’s selective deposition and nucleation techniques to cross-point MRAM structure and process of Wan et al., as modified by Hashemi et al., to selectively form material on exposed conductive regions while suppressing deposition on surrounding dielectric regions. This technique, as taught by Hou et al., of providing nucleation inhibition later on dielectric surfaces while leaving electrode surfaces exposed for selective deposition, allows formation of selector material only where needed, avoiding dielectric nucleation and suppresses unwanted or unnecessary selector growth on dielectric surfaces, thereby improving performance, reliability, and yield.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (US 11631716 B2) in view of Hashemi et al. (US 20200251652 A1) and Wan et al. (US 20210313392 A1).
Regarding claim 17, Wan et al. (US 11631716 B2) in view of Hashemi et al. teaches the method of claim 1. Wan et al. (US 11631716 B2) does not teach wherein the selector elements comprise portions of an ovonic threshold switch material that is deposited by physical vapor deposition.
However, Wan et al. (US 20210313392 A1) teaches wherein the selector elements (first selector material layer 502) comprise portions of an ovonic threshold switch material ([0093]) that is deposited by physical vapor deposition ([0094], PVD).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have employed Wan et al. (US 20210313392 A1)’s OTS selector material and PVD technique to the selector forming portion of Wan et al. (US 11631716 B2)’s cross-point MRAM fabrication process, as modified by Hashemi et al., because PVD is a known deposition technique for forming OTS selector material and is a predictable use of known material and deposition technique for its intended function.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wan et al. (US 11631716 B2) in view of Hashemi et al. (US 20200251652 A1), Hou et al. (CN 114766061 A), Ellinger et al. (US 8921236 B1), Prinz et al. (US 20190249301 A1), and Wan et al. (US 20210313392 A1).
Regarding claim 16, Wan et al. (US 11631716 B2) in view of Hashemi et al. and Hou et al. (CN 114766061 A) teach the method of claim 15. Wan et al. (US 11631716 B2) does not teach wherein the selective deposition process further comprises an oxygen plasma treatment step that removes ligands from the at least one monolayer of the ovonic threshold switch material and removes the layer of nucleation inhibitor molecules.
However, Ellinger et al. teaches wherein the selective deposition process ([0028]) further comprises an oxygen plasma treatment step ([0038], highly reactive oxygen-containing plasma process)
and removes (Figure 6d) the layer of nucleation inhibitor molecules ([0076], uniform polymer inhibitor layer 210).
And Prinz et al. teaches an oxygen plasma treatment step that removes ligands ([0041]) from the at least one monolayer of the ovonic threshold switch material (adsorbed first precursor).
However, Prinz et al. does not teach ovonic threshold switch material. Wan et al. (US 20210313392 A1) supplies one monolayer of the ovonic threshold switch material ([0093]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated Ellinger et al.’s and Prinz et al.’s oxygen-plasma treatment technique to Hou et al.’s selective deposition process, as applied to Wan et al.’s MRAM structure, to remove deposition inhibiting material and organic ligands after precursor adsorption. Specifically, employing Ellinger et al.’s highly reactive oxygen process to remove portions of inhibitor and Prinz et al.’s oxygen plasma used as oxidative precursor that reacts with adsorbed precursor to liberate organic ligands, would allow removal of unwanted inhibitor material and precursor ligands during deposition on surrounding dielectric while selectively forming selector material on electrode.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEANNE M KIM whose telephone number is (571)272-8768. The examiner can normally be reached Monday-Thursday 8:00-6:00.
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/JEANNE MYON KIM/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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