DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-10, 13-18, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Basu et al. (US 2021/0055935).
Claim 1, Basu discloses a circuit (100, Fig. 1), comprising:
a memory controller (memory apparatus 104, Fig. 1) operatively coupled between a host (HOST 102, Fig. 1) and a memory device (Memory Device 112-112-N, Fig. 1), and configured to receive an instruction signal from the host and provide the memory device with a programmable interface signal based on the instruction signal (see P[0025]-P[0027]);
wherein the memory controller comprises a programmable memory array (see P[0020]… The memory apparatus 104 can be a field programmable gate array (FPGA) including a non-persistent memory device, such as a DRAM and/or SRAM memory array…) comprising a plurality of memory cells (memory cells are inherent elements in the SRAM array), and wherein each of the plurality of memory cells is configured to store data in a format that has a plurality of programmable fields (see P[0015]… Each of the configurations of these memory elements can be associated with a different boot image so that the memory elements are configurable based on which boot image is used to boot up the memory apparatus…).
Claim 2, Basu discloses the circuit of claim 1, wherein the programmable interface signal includes at least one of: a level change with no cycle delay; an edge change with no cycle delay; a level change with a cycle delay (see P[0016]… a configurable FPGA can be configured to increase and/or decrease a latency of the data processing…); or an edge change with a cycle delay.
Claim 7, Basu discloses the circuit of claim 1, wherein a type of the memory device is at least one of: non-volatile memory, multi-time programmable memory (MTP), resistive random access memory or magneto-resistive random access memory (MRAM) (see P[0033]….memory devices 112 can include other non-volatile memory devices such as non-volatile random-access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), “emerging” memory devices such as variable resistance…).
Claim 8, Basu discloses the circuit of claim 1, wherein the programmable memory array is one of static random access memory (see P[0015], [0020]…SRAM…), read-only memory (ROM), or flip flops.
Claims 9-10 are rejected as above claims 1-2 because of similar elements and limitations.
Claim 13, Basu discloses the system of claim 9, wherein the memory controller further comprises at least one logic gate of: an inverse gate; an AND gate; an OR gate; or an XOR gate (see P[0015]… Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates such as AND, XOR….).
Claim 14, Basu discloses the system of claim 9, wherein the memory controller is configured to provide the programmable interface signal based on a function of inputs in the instruction signal, the function generated based on the at least one logic gate (see P[0015]… Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates such as AND, XOR….).
Claim 15, Basu discloses the system of claim 9, wherein a type of the memory device is at least one of: non-volatile memory, multi-time programmable memory (MTP), resistive random access memory (RRAM) or magneto-resistive random access memory (MRAM) (see P[0033]… memory devices 112 can include other non-volatile memory devices such as non-volatile random-access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), “emerging” memory devices such as variable resistance…).
Claim 16, Basu discloses the system of claim 9, wherein the programmable memory array is one of static random access memory (see P[0015], [0020]…SRAM…), read-only memory (ROM), or flip flops.
Claims 17-18, and 20 are rejected as above claims 1-2, and 13 because the elements and limitations are similar.
Allowable Subject Matter
Claims 3-6, 11-12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sharette et al. (US 2013/0279232) and Ogawa et al. (US 2007/0192527) disclose a system comprises a memory controller which can be an FPGA for providing interface between a computer and a plurality of non-volatile memory devices.
Atsatt et al. (US 2021/0011636) discloses an FPGA with configurable RAM.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander H Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANH Q TRAN/Primary Examiner, Art Unit 2844 2/13/26