Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on 04/23/2024 have been acknowledged and considered by examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 12, 13, and 18 are rejected under 35 U.S.C. 102 (a1) as being anticipated by US 20160356842 A1 (Lee).
With regards to claim 1, Lee teaches a probe card (A contactor system for testing integrated circuits ([0010])) comprising: a socket structure comprising at least one socket (“socket” [0010]); and a plane structure located on the socket structure ("Printed Circuit Board (PCB)" ([0010], [0036])),
wherein the at least one socket comprises: at least one radio frequency (RF) signal pin through which a signal of an RF band is transmitted (a socket used for "80 GHz millimeter wave test capability" ([0009])); and at least one ground pin, ("Signal pins" (314, 315) and "Ground pins" (312, 313). ([0038]))
and a plane structure comprises: an RF plane comprising at least one RF signal line electrically connected to the at least one RF signal pin (a "signal plane comprising signal traces" ([0010]). These traces (1026) are electrically connected to the signal pogo pins via "signal vias" (1025). ([0050], Fig. 10B));
and a ground plane electrically connected to the at least one ground pin, the ground plane being located between the RF plane and the socket structure (a ground plane (1028) that is "nearer to the second end [the socket interface] relative to the signal plane [1029]." ([0010]). Lee further clarifies the vertical stack-up: "configuring the ground plane 1028 to be above the plane with the signal traces 1029." ([0050], Fig. 10B).
With regards to claim 2, Lee teaches the probe card of claim 1, wherein the ground plane is located closer to a lower surface of the plane structure than the RF plane (a ground plane (1028) that is "nearer to the second end [the socket interface] relative to the signal plane [1029]." ([0010])), and comprises a conductive material to shield the signal of the at least one RF signal pin (Lee teaches that this layout “removes parasitic noise” [0052] and “minimizes the dielectric gap” [0053] to improve performance at 80 GHz and inherently shields the signal.)
With regards to claim 4, Lee teaches the probe card of claim 1, wherein the plane structure further comprises at least one first via connecting the at least one RF signal pin to the at least one RF signal line ("signal is communicated... through signal vias 1025" to reach the "signal traces 1026" ([0050]),
and the ground plane is in direct contact with the socket structure ("ground plane 1028 [is] to be above the plane with the signal traces 1029" and is "nearer to the second end [socket interface]" ([0010], [0050]). Since the ground plane is the layer "nearer" to the socket and receives ground signals immediately upon pin contact ([0052]), it is in direct contact with the socket structure).
With regards to claim 5, Lee teaches the probe card of claim 2, wherein the plane structure comprises: at least one first via connecting the at least one RF signal pin to the at least one RF signal line ("The signal is communicated... through signal vias 1025 and starts traveling across the PCB when it reaches the signal traces 1026." ([0050]));
and at least one second via connecting the at least one ground pin to the ground plane ("ground vias" 1015 ([0049]); "ground signals... reach the ground plane 1028 before the signal reaches the signal plane 1029." ([0050]),
and a vertical length of the at least one first via is greater than a vertical length of the at least one second via ("ground plane 1028 is above the plane with the signal traces 1029" relative to the pogo pins ([0050]). Since the pogo pins contact the PCB from the bottom, the signal must travel through a via that passes the ground plane to reach the deeper signal traces (1026). In contrast, the ground path terminates at the ground plane (1028) which is "nearer" to the pins ([0010]). Because the signal plane (1029) is deeper in the PCB than the ground plane (1028), the vertical length of the signal via (connecting to the deeper layer) is inherently greater than the vertical length of the ground via (connecting to the nearer layer)).
With regards to claim 12, Lee teaches a probe card comprising: a socket structure comprising a pogo pin socket; and a plane structure located on the socket structure ("socket" that utilizes "pogo pin connectors" ([0010]) and a "Printed Circuit Board (PCB)" (plane structure) consisting of "multiple layers" ([0049])),
wherein the plane structure includes a plurality of layers, wherein the pogo pin socket comprises a first ground pin, a second ground pin, a first radio frequency (RF) signal pin, and a second RF signal pin, through which a signal of an RF band is transmitted (Lee explicitly discloses a pogo pin configuration using a "GSSG" (Ground-Signal-Signal-Ground) configuration ([0038]). This configuration consists of a first and second Ground pin (312, 313) and a first and second Signal pin (314, 315) used for "80 GHz millimeter wave" (RF band) testing ([0009], [0038])),
the plane structure comprises a first RF signal line in a first layer electrically connected to the first RF signal pin, a second RF signal line in a second layer electrically connected to the second RF signal pin ("signal traces 1026" located on a "signal plane" ([0050]). In high-frequency differential routing (like Lee's GSSG), signal lines are inherently routed through specific layers (first and second layers) to reach the traces (1026)),
and a ground plane electrically connected to the first ground pin and the second ground pin ("ground plane 1028" that receives the "ground signals 1127" from the pogo pins ([0050], [0052])),
and the ground plane is located on a third layer closer to a lower surface of the plane structure than the first layer and the second layer, among the plurality of layers ("ground plane 1028 [is] to be above the plane with the signal traces 1029" ([0050]). Because the pogo pins enter the PCB from the "lower surface" (the socket structure), Lee's configuration where the ground plane (3rd layer) is "above" the signal layers (1st and 2nd layers) means it is physically closer to that lower surface. Lee notes this specifically to ensure ground signals reach the plane before signal reaches the traces to "reduce ground lag" ([0051]).
With regards to claim 13, Lee teaches the probe card of claim 12, wherein the third layer is in direct contact with the socket structure. ("ground plane 1028 [is] nearer to the second end [the pogo pin/socket interface] relative to a plane with signal traces." ([0010]). Lee further specifies that moving the ground plane to the surface facing the pogo pins results in the ground signal reaching the "ground plane 1128" immediately. ([0051], Fig. 11B). Since the ground plane (the 3rd layer) is the "nearer" layer relative to the socket structure, it serves as the physical landing surface. Therefore, the ground plane layer is in direct physical and electrical contact with the socket structure to minimize the distance ground signals must travel. ([0051] - [0052]).
With regards to claim 18, Lee teaches a semiconductor device inspection system comprising: a test apparatus comprising a test body and a test head; and a probe card configured to be controlled by the test apparatus (an automated testing equipment (ATE) apparatus used for high-frequency testing of integrated circuits ([0007], [0012]). Lee explicitly discloses a test system comprising a "test head of an ATE" communicating with a test body/tester 104 ([0012], [0016]) and a probe card (PCB 219) used as the interface to the device under test (DUT) ([0036])),
wherein the probe card comprises: a socket comprising a plurality of radio frequency (RF) signal pins through which a signal of an RF band is transmitted and a plurality of ground pins (a plurality of pogo pin connectors ([0010]). Lee discloses a "GSSG" (Ground Signal Signal Ground) pin configuration within the socket, where pins 314 and 315 are Signal pins for "80 GHz millimeter wave" signals and pins 312 and 313 are Ground pins ([0038]));
a plurality of RF signal lines electrically connected to the plurality of RF signal pins; and a ground plane electrically connected to the plurality of ground pins (the PCB includes "signal traces" (1026) that are electrically connected to the signal pogo pins ([0012], [0050]) and at least one "ground plane" (1028) electrically connected to the ground signals ([0010], [0050])), and
the plurality of RF signal lines are closer to a lower surface of the test apparatus than the ground plane (the PCB is configured such that the "ground plane 1028 is nearer to the second end [the pogo pin/socket interface] relative to the signal plane 1029" ([0010], [0050])).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20160356842 A1 (Lee) in view of US 7135643 B2 (Van Haaster).
With regards to claim 3, Lee identifies the need to manage noise at 80 GHz but relies on conductive shielding [0046].
However, Lee does not teach:
The probe card of claim 1, wherein the plane structure further comprises an absorption plane located between the RF plane and the ground plane that absorbs a leakage signal.
Van Haaster teaches an "electrically absorbing or lossy material" provided as a sheet or layer (Col. 3, lines 11-23). Van Haaster clarifies that this absorption is achieved through "ohmic loss," which dissipates energy into thermal heat rather than reflecting it back into the signal path (Col. 3, lines 11-23). Furthermore, Van Haaster explicitly teaches that placing this absorbing material within a conductive cavity, such as the space between the planes of a probe card, operates to "alter the resonant characteristics of the cavity to reduce resonant ‘peaks’" and "suppress EMI transmissions" (Col. 3, lines 11-23; Col. 5, line 66).
By adding Van Haaster’s absorption material, the system ensures that stray "leakage" energy is converted to heat rather than being reflected back into the signal path. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the absorption plane of Van Haaster into the high-frequency probe card structure of Lee wherein the plane structure further comprises an absorption plane located between the RF plane and the ground plane that absorbs a leakage signal because it is a known high-frequency damping technique (Van Haaster) to a known probe card architecture (Lee) to solve the known problem of signal resonance and leakage in the RF band.
With regards to claim 14, Lee identifies the need to manage noise at 80 GHz but relies on conductive shielding [0046].
However, Lee does not teach:
The probe card of claim 12, wherein the plane structure further comprises an absorption plane in contact with an upper surface of the ground plane that absorbs a leakage signal.
Van Haaster teaches an "electrically absorbing or lossy material" provided as a sheet or layer (Col. 3, lines 11-23). Van Haaster clarifies that this absorption is achieved through "ohmic loss," which dissipates energy into thermal heat rather than reflecting it back into the signal path (Col. 3, lines 11-23). Van Haaster discloses that “an electromagnetic absorbing material [is] disposed on a first side of the electrically-conductive shield” or "applied to a first side of an EMI enclosure [shield]" (Col. 3, lines 29-30; Col. 5, lines 44-45). In a multi-layer stack-up, applying the absorber to the surface of the shield (ground plane) that faces the signal source is a standard application method.
By adding Van Haaster’s absorption material, the system ensures that stray "leakage" energy is converted to heat rather than being reflected back into the signal path. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the absorption plane of Van Haaster into the multi-layer PCB structure of Lee wherein the plane structure further comprises an absorption plane in contact with an upper surface of the ground plane that absorbs a leakage signal. Lee provides the spatial arrangement of ground and signal layers. Van Haaster teaches that the most effective way to prevent resonant peaks and EMI reflections is to apply a lossy, absorbing material directly to the surface of the conductive shield: "applied to a first side". This configuration is a predictable application of known EMI suppression techniques to achieve the known benefit of reducing resonance in a high-frequency (80 GHz) test environment.
With regards to claim 20, Lee identifies the need to manage noise at 80 GHz but relies on conductive shielding [0046].
However, Lee does not teach:
The semiconductor device inspection system of claim 18, further comprising an absorption plane located between the plurality of RF signal lines and the ground plane that absorbs a leakage signal.
Van Haaster teaches an "electrically absorbing or lossy material" provided as a sheet or layer (Col. 3, lines 11-23). Van Haaster clarifies that this absorption is achieved through "ohmic loss," which dissipates energy into thermal heat rather than reflecting it back into the signal path (Col. 3, lines 11-23). Furthermore, Van Haaster explicitly teaches that placing this absorbing material within a conductive cavity, such as the space between the planes of a probe card, operates to "alter the resonant characteristics of the cavity to reduce resonant ‘peaks’" and "suppress EMI transmissions" (Col. 3, lines 11-23; Col. 5, line 66).
By adding Van Haaster’s absorption material, the system ensures that stray "leakage" energy is converted to heat rather than being reflected back into the signal path. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the absorption plane of Van Haaster into the semiconductor inspection system of Lee wherein it further comprises an absorption plane located between the plurality of RF signal lines and the ground plane that absorbs a leakage signal because it is a known high-frequency damping technique (Van Haaster) to a known probe card architecture (Lee) to solve the known problem of signal resonance and leakage in the RF band.
Claims 6, 8, 9, 10, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US 20160356842 A1 (Lee) in view of US 20210302472 A1 (Ahn).
With regards to claim 6, Lee does not teach:
The probe card of claim 1, wherein the at least one ground pin is located closer to a side surface of the at least one socket than the at least one RF signal pin.
However, Ahn teaches a probe head and probe card designed to block signal interference by forming a shield portion at a periphery of a guide hole ([0011]). Ahn discloses a configuration where "the shield portion 60 may be provided at the periphery of the guide hole GH in which a signal probe 80A is provided" ([0112]).
While Lee provides a vertical ground plane to suppress resonance ([0050]- [0052]), Ahn teaches that lateral signal interference is blocked by positioning ground structures (shielding and ground probes) around the signal probe ([0182]- [0184]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the socket of Lee with the peripheral grounding logic of Ahn wherein the at least one ground pin is located closer to a side surface of the at least one socket than the at least one RF signal pin to provide a "shielding cage" effect and improve the reliability of Lee’s 80 GHz testing by combining Lee's vertical noise suppression with Ahn's lateral EMI blocking.
With regards to claim 8, Lee does not teach:
The probe card of claim 6, wherein the at least one ground pin is in direct contact with the side surface of the at least one socket.
However, Ahn teaches a probe head where the shield portion 60 is formed within the guide plate GP ([0110]). Ahn discloses that this shielding structure can be formed by "filling pores of an anodic oxide film" ([0015]) or by "filling the etching hole with a metal material" ([0016]). Ahn teaches that these conductive structures (which are grounded) are in contact with the guide plate which forms the socket structure. Specifically, Ahn mentions the shield portion can be grounded by itself ([0184]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the socket of Lee with the peripheral grounding logic of Ahn wherein the at least one ground pin is in direct contact with the side surface of the at least one socket to ensure a common ground potential and to maximize lateral EMI containment. This modification predictably improves the reliability of Lee’s 80 GHz testing by combining Lee's vertical noise suppression with Ahn's lateral EMI blocking.
With regards to claim 9, Lee teaches the probe card of claim 6, wherein the plane structure further comprises: at least one first via connecting the at least one RF signal pin to the at least one RF signal line; ("The signal is communicated... through signal vias 1025 and starts traveling across the PCB when it reaches the signal traces 1026." ([0050]))
and at least one second via connecting the at least one ground pin to the at least one ground plane ("ground vias" 1015 ([0049]); "ground signals... reach the ground plane 1028 before the signal reaches the signal plane 1029." ([0050]).
With regards to claim 10, Lee does not explicitly disclose that the RF plane is in direct contact with an upper surface of the plane structure.
However, Lee teaches a layered stack-up where the ground plane 1028 is closer to the socket, and the signal traces 1026 are on a "signal plane 1029" ([0050]) located at the end opposite the pogo pins ([0010]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the RF plane of Lee at the upper surface of the plane structure (the surface furthest from the socket). In the probe card architecture of Lee, the signal travels from the DUT (bottom) through the PCB to the Test Head (top). Placing the RF plane at the upper surface is a predictable design choice to facilitate the shortest possible connection to the testing apparatus while maintaining the ground plane's proximity to the socket as required by Lee's anti-resonance logic.
With regards to claim 15, Lee does not teach:
The probe card of claim 12, wherein the first ground pin is closer to a side surface of the pogo pin socket than the first RF signal pin, and the second ground pin is closer to the side surface of the pogo pin socket than the second RF signal pin.
However, Ahn teaches a probe head pin arrangement where ground probes 80B are positioned at the periphery of signal probes 80A ([0120], [0124]). Specifically, Ahn discloses forming a shield portion 60 at the periphery of signal pins and suggests that ground probes are inserted into guide holes "formed at the outside of the shield portion 60" ([0120]). Ahn further teaches that lateral signal interference is blocked by positioning ground structures (shielding and ground probes) around the signal probe ([0182]- [0184]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the socket of Lee with the peripheral grounding logic of Ahn wherein the first ground pin is closer to a side surface of the pogo pin socket than the first RF signal pin, and the second ground pin is closer to the side surface of the pogo pin socket than the second RF signal pin to provide a "shielding cage" effect. This modification predictably improves the reliability of Lee’s 80 GHz testing by combining Lee's vertical noise suppression with Ahn's lateral EMI blocking.
With regards to claim 17, Lee does not explicitly disclose that the first and second layers are in direct contact with an upper surface of the plane structure. However, Lee teaches a layered stack-up where the ground plane 1028 is closer to the socket, and the signal traces 1026 are on a "signal plane 1029" ([0050]) located at the end opposite the pogo pins ([0010]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the signal layers of Lee at the upper surface of the plane structure (the surface furthest from the socket). In the probe card architecture of Lee, the signal travels from the DUT (bottom) through the PCB to the Test Head (top). Placing the signal layers (Layer 1 and Layer 2) at the upper surface is a predictable design choice to facilitate the shortest possible connection to the testing apparatus while maintaining the ground plane's proximity to the socket as required by Lee's anti-resonance logic.
Claims 7, 16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 20160356842 A1 (Lee) in view of US 20210302472 A1 (Ahn) and further in view of TW 201331589 A (Gu).
With regards to claim 7, Lee as modified by Ahn does not teach:
The probe card of claim 6, wherein the at least one ground pin is in direct contact with the at least one RF signal pin.
However, Gu teaches a high-power RF probe card 100 comprising a first signal pin 18 and a second signal pin 20 where the tail of the second pin 20b is "electrically connected to the first signal pin 18 by a solder 22" ([16]). Gu further teaches a ground pin 28 that is electrically connected to matching components 24, 30, 44 that are "integrated on the structure of the first signal pin 18" ([19]). Specifically, Gu discloses that a conductive surface layer 44 or matching wire 24 is "formed on the surface" or "covers" the signal pin ([22]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the pin layout of Lee as modified by Ahn to incorporate the teachings of Gu wherein the at least one ground pin is in direct contact with the at least one RF signal pin to "avoid bandwidth attenuation due to the parallel effect" ([19]) while maintaining a "good bandwidth" for RF testing ([19]).
With regards to claim 16, Lee does not teach:
The probe card of claim 15, wherein the first ground pin and the second ground pin are in direct contact with the side surface of the pogo pin socket, the first RF signal pin is in direct contact with the first ground pin, and the second RF signal pin is in direct contact with the second ground pin.
However, Ahn teaches a probe head where the shield portion 60 is formed within the guide plate GP ([0110]). Ahn discloses that this shielding structure can be formed by "filling pores of an anodic oxide film" ([0015]) or by "filling the etching hole with a metal material" ([0016]). Ahn teaches that these conductive structures (which are grounded) are in contact with the guide plate which forms the socket structure. Specifically, Ahn mentions the shield portion can be grounded by itself ([0184]).
Gu further teaches a high-power RF probe card 100 comprising a first signal pin 18 and a second signal pin 20 where the tail of the second pin 20b is "electrically connected to the first signal pin 18 by a solder 22" ([16]). Gu further teaches a ground pin 28 that is electrically connected to matching components 24, 30, 44 that are "integrated on the structure of the first signal pin 18" ([19]). Specifically, Gu discloses that a conductive surface layer 44 or matching wire 24 is "formed on the surface" or "covers" the signal pin ([22]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the socket of Lee to implement the direct contact points taught by Ahn and Gu wherein the first ground pin and the second ground pin are in direct contact with the side surface of the pogo pin socket, the first RF signal pin is in direct contact with the first ground pin, and the second RF signal pin is in direct contact with the second ground pin to provide a "shielding cage" effect and "avoid bandwidth attenuation due to the parallel effect" ([19]).
With regards to claim 19, Lee does not teach:
The semiconductor device inspection system of claim 18, wherein the plurality of ground pins are in direct contact with a side surface of the socket, and the plurality of RF signal pins are in direct contact with the plurality of ground pins.
However, Ahn teaches a probe head where the shield portion 60 is formed within the guide plate GP ([0110]). Ahn discloses that this shielding structure can be formed by "filling pores of an anodic oxide film" ([0015]) or by "filling the etching hole with a metal material" ([0016]). Ahn teaches that these conductive structures (which are grounded) are in contact with the guide plate which forms the socket structure. Specifically, Ahn mentions the shield portion can be grounded by itself ([0184]).
Gu further teaches a high-power RF probe card 100 comprising a first signal pin 18 and a second signal pin 20 where the tail of the second pin 20b is "electrically connected to the first signal pin 18 by a solder 22" ([16]). Gu further teaches a ground pin 28 that is electrically connected to matching components 24, 30, 44 that are "integrated on the structure of the first signal pin 18" ([19]). Specifically, Gu discloses that a conductive surface layer 44 or matching wire 24 is "formed on the surface" or "covers" the signal pin ([22]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the socket of Lee to implement the direct contact points taught by Ahn and Gu wherein the plurality of ground pins are in direct contact with a side surface of the socket, and the plurality of RF signal pins are in direct contact with the plurality of ground pins to provide a "shielding cage" effect to "avoid bandwidth attenuation due to the parallel effect" ([19]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over US 20160356842 A1 (Lee) in view of US 20210302472 A1 (Ahn) and US 7135643 B2 (Van Haaster).
With regards to claim 11, Lee identifies the need to manage noise at 80 GHz but relies on conductive shielding [0046].
However, Lee as modified by Ahn does not teach:
The probe card of claim 6, wherein the plane structure further comprises an absorption plane located between the RF plane and the ground plane that absorbs a leakage signal.
Van Haaster teaches an "electrically absorbing or lossy material" provided as a sheet or layer (Col. 3, lines 11-23). Van Haaster clarifies that this absorption is achieved through "ohmic loss," which dissipates energy into thermal heat rather than reflecting it back into the signal path (Col. 3, lines 11-23). Furthermore, Van Haaster explicitly teaches that placing this absorbing material within a conductive cavity, such as the space between the planes of a probe card, operates to "alter the resonant characteristics of the cavity to reduce resonant ‘peaks’" and "suppress EMI transmissions" (Col. 3, lines 11-23; Col. 5, line 66).
By adding Van Haaster’s absorption material, the system ensures that stray "leakage" energy is converted to heat rather than being reflected back into the signal path. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the absorption plane of Van Haaster into the high-frequency probe card structure of Lee wherein the plane structure further comprises an absorption plane located between the RF plane and the ground plane that absorbs a leakage signal because it is a known high-frequency damping technique (Van Haaster) to a known probe card architecture (Lee) to solve the known problem of signal resonance and leakage in the RF band.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 7456646 B2 (Hayden)
US 20120235697 A1 (Jang)
US 20100283495 A1 (Yoo)
US 5565788 A (Burr)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSAMAH MURSHED whose telephone number is (571)272-9534. The examiner can normally be reached Monday - Friday, 11 a.m. 8 p.m. ET..
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/OSAMAH MURSHED/ Examiner, Art Unit 2858
/JUDY NGUYEN/ Supervisory Patent Examiner, Art Unit 2858