DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 2 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Specifically, claim 2 recites a limitation that is different than what is found in the specification. While it states that the word line contact plug (281b) is connected to the first connecting extending part (WL_CE1) of the word line, the specification and drawings indicate that the plug is connected to the second connecting extending part (WL_CE2, Fig. 4).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 8, 11, 12, 14, 16, 19, and 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim fails to clarify the meaning of “between” in line 25 pertaining to the second connecting extending part (WL_CE2) and the electrode part (WL_E) of the word line (WL1). In conjunction with Fig. 10 of the drawings, the claim fails to make sense of the provided specification.
Regarding claim 8, the claim fails to clarify the meaning of “between” in reference to the first connecting extending part of the word line (WL_CE1), and the specification does not provide support for this limitation.
Regarding claim 11, the limitation of “first direction” is specified but not clarified as the claim recites a combination of features in Fig. 2 and 4 of the drawings. Similarly, the orientation recited is unclear since “a plurality of shielding conductive protruding patterns” is rendered meaningless with respect to both figures.
Regarding claim 12, the claim fails to clarify the meaning of “between” in the last two paragraphs of the claim pertaining to the second connecting extending part (WL_CE2), the electrode part (WL_E), and the first connecting extending part (WL_CE1) of the word lines. In conjunction with Fig. 10 of the drawings, the claim fails to make sense of the provided specification.
Regarding claim 14 and 16, the meaning of “adjacent to each other in the first direction” (line 4 of each claim) is unclear since this limitation is inconsistent with the directions provided in the specification and drawings, particularly in reference to the second active patterns (line 7 of each claim) that appear to be adjacent to both the first and second electrodes according to the drawings rather than only one particular electrode.
Regarding claim 19, directions are unclear as they are inconsistent with the specification and drawings. Also, the orientation of “shielding conductive protruding parts” (line 4 of the claim) is unclear as the limitation appears to conflate Fig. 2 and 4 of the provided drawings.
Regarding claim 20, the claim fails to clarify the meaning of “between” in reference to the second connecting extending part (WL_CE2) of the word lines, the cell region separation film (STI), and the active pattern separation structure (APBK). Fig. 18 shows all three elements but the limitation of the claim does not specify the orientation intended by “between.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tung et al. (2022/0122984, hereafter Tung) in view of Lee et al. (2024/0147701, hereafter Lee).
Regarding claim 1, Tung discloses a semiconductor memory device comprising: a cell region element separation film (112, Fig. 1-2, par. 0021) that is on a substrate (110, Fig. 1-2, par. 0021) and comprises a first cell region side wall and a second cell region side wall, wherein the first cell region side wall extends in a first direction, and wherein the second cell region side wall extends in a second direction (Fig. 1); an active pattern (113, Fig. 1, par. 0021) that is on the substrate and comprises a first side wall and a second side wall that are opposite to each other in the first direction and a first side and a second side that are opposite to each other in a third direction, wherein the first side of the active pattern faces the substrate (Fig. 1); a word line (130, Fig. 1, par. 0020) that is on the first side wall of the active pattern and extends in the second direction; a back gate electrode (135, Figs. 1, 2; par. 0022) that is on the second side wall of the active pattern and extends in the second direction; a bit line (150, Fig. 1, par. 0020) that is electrically connected (160, Fig. 1, par. 0023) to the first side of the active pattern and extends in the first direction; wherein the word line comprises an electrode part (130, Fig. 1, par. 0020) that extends in the second direction and along the back gate electrode, wherein the word line comprises a plug connecting part (333, Fig. 10, par. 0040) that extends beyond the back gate electrode in the second direction, wherein the plug connecting part of the word line comprises a first connecting extending part (333 left, Fig. 10) that extends in the first direction and a second connecting extending part (333 middle, Fig. 10) that extends in the second direction, and wherein the second connecting extending part of the word line is between the electrode part of the word line and the first connecting extending part of the word line.
Tung fails to disclose a data storage pattern that is electrically connected to the second side of the active pattern.
However, Lee teaches a data storage pattern (DSP, Fig. 1A, par. 0076) that is electrically connected to the second side of the active pattern.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by electrically connecting a data storage pattern to the active pattern in order to allow the access transistor to route, read, and write data signals while preventing electrical instability and cross-talk.
Regarding claim 2, Tung discloses a semiconductor memory device further comprising a word line contact plug (370, Fig. 10, par. 0040) that is electrically connected to the word line (330, Fig. 10), wherein the word line contact plug is electrically connected to the first connecting extending part of the word line.
Regarding claim 3, Tung discloses a semiconductor memory device wherein the first connecting extending part (333 left, Fig. 10) of the word line (330, Fig. 10) extends from the second side wall of the active pattern (113, Fig. 10) and toward the first side wall of the active pattern.
Regarding claim 4, Tung discloses a semiconductor memory device wherein the first connecting extending (333 left, Fig. 10) part of the word line extends from the first side wall of the active pattern (113, Fig. 10) to the second side wall of the active pattern.
Regarding claim 5, Tung discloses a semiconductor memory device wherein the plug connecting part (333, Fig. 10) of the word line (330, Fig. 10) further comprises a third connecting extending part (333 right, Fig. 10) that is electrically connected to the first connecting extending part (333 left, Fig. 10) of the word line and extends in the second direction and toward the back gate electrode (135/330, Figs. 2, 10, par. 0022).
Regarding claim 6, Tung discloses the second connecting extending part (333 middle, Fig. 10) of the word line (330, Fig. 10).
Tung fails to disclose a semiconductor memory device further comprising an active pattern separation structure, wherein: a terminal end of the back gate electrode faces the active pattern separation structure, extends along a side wall of the active pattern separation structure.
However, Lee teaches a semiconductor memory device further comprising an active pattern separation structure (300, Fig. 1A, par. 0062), wherein: a terminal end of the back gate electrode (BG, Fig. 1A) faces the active pattern separation structure, extends along a side wall of the active pattern separation structure.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing an active pattern separation structure such that the back gate terminal end faces it in order to provide a dielectric barrier that prevents electrical leakage, minimizes parasitic capacitance, and confines back gate biasing field away from adjacent active circuits.
Regarding claim 7, Tung discloses a semiconductor memory device wherein the first connecting extending (333 left, Fig. 10) part of the word line (330, Fig. 10).
Tung fails to disclose extends along the side wall of the active pattern separation structure.
However, Lee teaches extends along the side wall of the active pattern separation structure (300, Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by extending the first connecting extending part along the active pattern separation structure in order to provide a compact, low-resistance guard ring that maximizes contact area, clamps potential, and shields circuits from electrical noise.
Regarding claim 8, Tung discloses the first connecting extending part (333 left, Fig. 10) of the word line (330, Fig. 10).
Tung fails to disclose a semiconductor memory device wherein: the active pattern separation structure contacts the cell region element separation film, … is not between the active pattern separation structure and the cell region element separation film.
However, Lee teaches a semiconductor memory device wherein: the active pattern separation structure (300 in WCR, Fig. 1A, par. 0062) contacts the cell region element separation film (STI in WCR, Fig. 1A, par. 0082), … is not between the active pattern separation structure and the cell region element separation film.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing an active pattern separation film contacts the cell region element separation film in order to create a continuous dielectric barrier, thus eliminating parasitic leakage.
Regarding claim 11, Tung fails to disclose a semiconductor memory device further comprising a shielding conductive pattern disposed on the substrate, wherein: the shielding conductive pattern comprises a shielding conductive plate and a plurality of shielding conductive protruding patterns that extend from the shielding conductive plate in the first direction, and the bit line is between two adjacent shielding conductive protruding patterns of the plurality of shielding conductive protruding patterns.
However, Lee teaches a semiconductor memory device further comprising a shielding conductive pattern (173, Fig. 1A, par. 0026) disposed on the substrate, wherein: the shielding conductive pattern comprises a shielding conductive plate (173b, Fig. 2B, par. 0032) and a plurality of shielding conductive protruding patterns (173a, Fig. 2B, par. 0032) that extend from the shielding conductive plate in the first direction, and the bit line (BL, Fig. 1A, par. 0026) is between two adjacent shielding conductive protruding patterns of the plurality of shielding conductive protruding patterns.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing a shielding conductive pattern with protrusions from the plate in order to prevent cross-talk between circuits, with protrusions extending into small spaces to isolate wires locally.
Regarding claim 12, Tung discloses a semiconductor memory device comprising: a cell region element separation film (112, Fig. 10, par. 0021) that is on a substrate (110, Fig. 10, par. 0021) and comprises a first cell region side wall and a second cell region side wall, wherein the first cell region side wall extends in a first direction, and wherein the second cell region side wall extends in a second direction (Fig. 10, par. 0026); back gate electrodes (135, Fig. 2, par. 0022) that are on the substrate and extend in the second direction; a first word line (330 left, Fig. 10, par. 0039) and a second word line (330 right, Fig. 10); active patterns (113, Fig. 10, par. 0021) that are between the second word line and the first word line and that are spaced apart in the second direction; bit lines (350, Fig. 10, par. 0039) that are between the substrate and the first and second word lines and that extend in the first direction; wherein each of the first word line and the second word line comprises an electrode part (330, Fig. 10) that extends in the second direction and along the back gate electrodes and a plug connecting part (333, Fig. 10) that extends from the back gate electrodes and in the second direction, wherein each of the plug connecting part of the first word line and the plug connecting part of the second word line comprises a first connecting extending part (333 left/331 right, Fig. 10) that extends in the first direction and a second connecting extending (333 middle/331 middle, Fig. 10) part that extends in the second direction, wherein the second connecting extending part of the first word line is between the electrode part of the first word line and the first connecting extending part of the first word line, and wherein the second connecting extending part of the second word line is between the electrode part of the second word line and the first connecting extending part of the second word line (Fig. 10).
Tung fails to disclose, that are between the back gate electrodes and extend in the second direction; and a data storage pattern that is on and electrically connected to the active patterns.
However, Lee teaches that are between the back gate electrodes (BG, Fig. 1A, par. 0044) and extend in the second direction; and a data storage pattern (DSP, Fig. 1A, par. 0076) that is on and electrically connected to the active patterns (AP1/2, Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing alternating back gate electrodes and a data storage pattern on the active patterns in order to eliminate electrical leakage and crosstalk, while maximizing space and access to the active channel.
Regarding claim 13, Tung discloses a semiconductor memory device wherein: each of the first word line (333 left, Fig. 10) and the second word line (333, right, Fig. 10) further comprises an electrode extending part (330 bottom end, Fig. 10); the electrode part (330, Fig. 10) of the first word line is between the plug connecting part (333, Fig. 10) of the first word line and the electrode extending part of the first word line, the electrode part (330, Fig. 10) of the second word line is between the plug connecting part (331, Fig. 10, par. 0040) of the second word line and the electrode extending part of the second word line (330 top end, Fig. 10), and the plug connecting part of the first word line overlaps the plug connecting part of the second word line in the first direction (Fig. 10).
Tung fails to disclose, that extends beyond the back gate electrodes in the second direction.
However, Lee teaches that extends beyond the back gate electrodes (BG, Fig. 1A) in the second direction.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing an extending part that extends beyond the back gate electrodes in order to create a distinct landing pad for contacts while ensuring electric field activates the channel without leaving dead zones.
Regarding claim 14, Tung discloses, the first connecting extending part (333 left, Fig. 10) of the first word line (330 left, Fig. 10) overlaps the first back gate electrodes (135, Fig. 2, par. 0022) in the second direction, and the first connecting extending part (331 right, Fig. 10) of the second word line overlaps the second back gate electrode in the second direction.
Tung fails to disclose a semiconductor memory device wherein: the active patterns comprise first active patterns and second active patterns, wherein the back gate electrodes comprise a first back gate electrode and a second back gate electrode that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line, the second active patterns are between the second back gate electrode and the second word line.
However, Lee teaches a semiconductor memory device wherein: the active patterns comprise first active patterns (AP1, Fig. 1A, par. 0037) and second active patterns (AP2, Fig. 1A, par. 0037), wherein the back gate electrodes (BG, Fig. 1A) comprise a first back gate electrode (upper) and a second back gate electrode (lower) that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line (WL1, Fig. 1A), the second active patterns are between the second back gate electrode and the second word line (WL2, Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing active patterns between the word lines and back gate electrodes in order to serve as physical channel layers, allowing gates to control the flow of charge from opposite sides for maximum switching efficiency and leakage prevention.
Regarding claim 15, Tung discloses a semiconductor memory device wherein: each of the first word line (330 left, Fig. 10) and the second word line (330 right, Fig. 10) further comprises an electrode extending part (330 end, Fig. 10) that extends, the electrode part (330 left, Fig. 10) of the first word line is between the plug connecting part (333, Fig. 10) of the first word line and the electrode extending part of the first word line, the electrode part (330 right, Fig. 10) of the second word line is between the plug connecting part (331, Fig. 10) of the second word line and the electrode extending part (330 right end, Fig. 10) of the second word line, the plug connecting part (333) of the first word line overlaps the electrode extending part of the second word line in the first direction, and the plug connecting part (331) of the second word line overlaps the electrode extending part of the first word line in the first direction (Fig. 10).
Tung fails to disclose, beyond the back gate electrodes in the second direction.
However, Lee teaches beyond the back gate electrodes (BC, Fig. 1A) in the second direction.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing an extending part that extends beyond the back gate electrodes in order to create a distinct landing pad for contacts while ensuring electric field activates the channel without leaving dead zones.
Regarding claim 16, Tung discloses, the first connecting extending part (333 left, Fig. 10) of the first word line (330 left, Fig. 10) overlaps the first back gate electrodes (135, Fig. 2, par. 0022) in the second direction, and the first connecting extending part (331 right, Fig. 10) of the second word line overlaps the second back gate electrode in the second direction.
Tung fails to disclose a semiconductor memory device wherein: the active patterns comprise first active patterns and second active patterns, the back gate electrodes comprise a first back gate electrode and a second back gate electrode that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line, the second active patterns are between the second back gate electrode and the second word line.
However, Lee teaches a semiconductor memory device wherein: the active patterns comprise first active patterns (AP1, Fig. 1A, par. 0037) and second active patterns (AP2, Fig. 1A, par. 0037), the back gate electrodes (BG, Fig. 1A) comprise a first back gate electrode (upper) and a second back gate electrode (lower) that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line (WL1, Fig. 1A), the second active patterns are between the second back gate electrode and the second word line (WL2, Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing active patterns between the word lines and back gate electrodes in order to serve as physical channel layers, allowing gates to control the flow of charge from opposite sides for maximum switching efficiency and leakage prevention.
Regarding claim 17, Tung discloses the first connecting extending part (233 left, Fig. 9, par. 0035) of the first word line does not overlap the first back gate electrode (135, Fig. 2, par. 0022) in the second direction, and the first connecting extending part (231 right, Fig. 9, par. 0035) of the second word line does not overlap the second back gate electrode in the second direction.
Tung fails to disclose a semiconductor memory device wherein: the active patterns comprise first active patterns and second active patterns, the back gate electrodes comprise a first back gate electrode and a second back gate electrode that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line, the second active patterns are between the second back gate electrode and the second word line.
However, Lee teaches a semiconductor memory device wherein: the active patterns comprise first active patterns (AP1, Fig. 1A) and second active patterns (AP2, Fig. 1A), the back gate electrodes comprise a first back gate electrode (BG above, Fig. 1A) and a second back gate electrode (BG below, Fig. 1A) that are adjacent to each other in the first direction, the first active patterns are between the first back gate electrode and the first word line (WL1, Fig. 1A), the second active patterns are between the second back gate electrode and the second word line (WL2, Fig. 1A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by implementing first connecting extending parts of the word lines that do not overlap the back gate electrode in order to provide an isolated landing zone for contacts, ensuring connection without shorting into the gate electrode.
Regarding claim 18, Tung discloses a semiconductor memory device further comprising: a first word line contact plug (370, Fig. 10) electrically connected (par. 0039) to the first connecting extending part of the first word line (333 left, Fig. 10), and a second word line contact plug (370, Fig. 10) electrically connected (par. 0039) to the first connecting extending part of the second word line (331 right, Fig. 10).
Regarding claim 19, Tung discloses bit lines (350, Fig. 10, par. 0039) that are on the shielding conductive pattern and extend in the first direction; a cell region element separation film (112, Fig. 10, par. 0021) that is on the peri-gate structure; back gate electrodes (135, Fig. 2, par. 0022) that are on the bit lines and extend in a second direction, wherein the back gate electrodes comprise a first back gate electrode and a second back gate electrode; a first word line (330 left, Fig. 10, par. 0039) and a second word (330 right, Fig. 10, par. 0039) line that are on the bit line, between the back gate electrodes, between the active pattern separation structures, and extend in the second direction; a first word line contact plug (370 top, Fig. 10) electrically connected to the first word line(par. 0039); a second word line contact plug (370 bottom, Fig. 10) electrically connected to the second word line (par. 0039); wherein each of the first word line and the second word line comprises a plug connecting part (333/331, Fig. 10) that extends beyond the back gate electrodes in the second direction, wherein each of the plug connecting part of the first word line and the plug connecting part of the second word line comprises a first connecting extending part (333 left/331 right, Fig. 10) that extends in the second direction along a side wall of the active pattern separation structure, a second connecting extending part (333 middle/331 middle, Fig. 10) that is electrically connected to the first connecting extending part and that extends in the first direction, and a third connecting extending part (333 right/331 left, Fig. 10) that is electrically connected to the second connecting extending part and that extends in the second direction, wherein the first word line contact plug is electrically connected to the second connecting extending part of the first word line, and wherein the second word line contact plug is electrically connected to the second connecting extending part of the second word line (par. 0039).
Tung fails to disclose a semiconductor memory device comprising: a peri-gate structure on a substrate; a shielding conductive pattern that is on the peri-gate structure and comprises a shielding conductive plate and a plurality of shielding conductive protruding parts that extend from the shielding conductive plate in a first direction; active pattern separation structures on opposing sides of the back gate electrode; first active patterns that are between the first back gate electrode and the first word line, electrically connected to the bit line, and spaced apart in the second direction; second active patterns that are between the second back gate electrode and the second word line, electrically connected to the bit line, and spaced apart in the second direction; and a data storage pattern that is on and electrically connected to the first active pattern and the second active pattern.
However, Lee teaches a semiconductor memory device comprising: a peri-gate structure (PG, Fig. 1B, par. 0070) on a substrate (200, Fig. 1B); a shielding conductive pattern (173, Fig. 1B, par. 0026) that is on the peri-gate structure and comprises a shielding conductive plate (173b, Fig. 2B, par.0032) and a plurality of shielding conductive protruding parts (173a, Fig. 2B, par. 0032) that extend from the shielding conductive plate in a first direction; active pattern separation structures (300, Fig. 1A, par. 0062) on opposing sides of the back gate electrode (BG, Fig. 1A); first active patterns (AP1, Fig. 1A, par. 0037) that are between the first back gate electrode and the first word line (WL1, Fig. 1A), electrically connected to the bit line (BL, Fig. 1A), and spaced apart in the second direction; second active patterns (AP2, Fig. 1A, par. 0037) that are between the second back gate electrode and the second word line (WL2, Fig. 1A), electrically connected to the bit line, and spaced apart in the second direction; and a data storage pattern (DSP, Fig. 1A, par. 0076) that is on and electrically connected to the first active pattern and the second active pattern.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by implementing a peri-gate structure and a shielding conductive pattern with active patterns and data storage patterns in order to create high-density memory architecture that balances storage capacity and data integrity.
Regarding claim 20, Tung discloses the second connecting extending part (333 middle, Fig. 10) of the first word line (330 left, Fig. 10) and the second connecting extending part (331 middle, Fig. 10) of the second word (330 right, Fig. 10) line are not between the active pattern separation structures and the cell region element separation film.
Tung fails to disclose a semiconductor memory device wherein: the active pattern separation structures contact the cell region element separation film.
However, Lee teaches a semiconductor memory device wherein: the active pattern separation structures (300, Fig. 1A, par. 0062) contact the cell region element separation film (STI, Fig. 1D, par. 0082).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung with Lee by providing active pattern separation structures that contact the cell region element separation film in order to create a continuous dielectric barrier that prevents electrical leakage between memory blocks while maximizing structural stability.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tung in view of Lee as applied to claim 1 above, and further in view of Taniguchi et al. (2015/0228658, hereafter Taniguchi).
Regarding claim 9, Tung and Lee fail to disclose a semiconductor memory device further comprising a dummy boundary word line that extends along the second side wall of the cell region element separation film.
However, Taniguchi teaches a semiconductor memory device further comprising a dummy boundary word line (47, Fig. 6, par. 0056) that extends along the second side wall of the cell region element separation film (53, Fig. 7, par. 0057).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung and Lee with Taniguchi by implementing a dummy boundary word line along the cell region element separation film in order to provide an electrical buffer that protects from peripheral noise cross-talk, stabilizes edge-leakage, and ensures uniform capacitive loading.
Regarding claim 10, Tung and Lee fail to disclose a semiconductor memory device wherein the dummy boundary word line does not extend along the first side wall of the cell region element separation film.
However, Taniguchi teaches a semiconductor memory device wherein the dummy boundary word line (47, Fig. 6) does not extend along the first side wall of the cell region element separation film (53, Fig. 7).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Tung and Lee with Taniguchi by implementing a dummy boundary word line along the cell region element separation film in order to provide an electrical buffer that protects from peripheral noise cross-talk, stabilizes edge-leakage, and ensures uniform capacitive loading.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tang (20240098966), pertaining to plug connecting parts and connecting extending parts.
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/C.M.B./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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