Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 07/07/2026. Currently, claims 1-20 are pending in the application. Claims 9 and 12-19 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Group I and Species IB (Figures 1 and 3), claims 1-8, 10-11 and 20, in the reply filed on 07/07/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM (KR 20200073550 A). An English translation of KIM is provided with this office action.
Regarding claim 1, Figure 2 of KIM discloses a display panel (AA), comprising
a hole-punch region (HA, Page 5, English translation), a display region (EA) surrounding the hole-punch region and an isolation region (BA) located between the display region and the hole-punch region;
wherein the display panel further comprises a base substrate (101), an array layer (112-104) and a light-emitting functional layer (130, Page 5, English translation), the array layer and the light-emitting functional layer are sequentially located on a side of the base substrate, wherein the array layer (112-104) further comprises a first insulating layer (112);
the light-emitting functional layer comprises a cathode (136), and the cathode extends from the display region to the isolation region (BA); and
a groove (110, Page 5, English translation) is provided in the isolation region (BA), and the groove penetrates at least part of the first insulating layer (112);
the groove comprises a first groove division (bottom portion) and a second groove division (middle portion) which are communicated with each other, and the second groove division is located on a side of the first groove division facing away from the base substrate; and
along a direction pointing from the display region (EA) to the hole-punch region (HA), a maximum length of the first groove division (bottom region of 110) is greater than a maximum length of the second groove division (middle region of 110), and the cathode (136) is disconnected at the groove (110).
Regarding claim 2, Figure 2 of KIM discloses that the display panel according to claim 1, wherein an angle between a bottom surface of the first groove division (bottom region of 110) and a side wall of the first groove division is θ, wherein 0<θ<90° (based on the drawing the sidewall of 110 is inclined).
Regarding claim 3, Figure 2 of KIM discloses that the display panel according to claim 1, wherein the display panel further comprises a barrier layer (154, Page 2, English translation), and the barrier layer is located on a side of the first insulating layer (112) facing away from the base substrate; and the second groove division (middle region of 110) penetrates the barrier layer (154), and a vertical projection of the second groove division on the base substrate (101) is located within a vertical projection of the first groove division on the base substrate.
Regarding claim 20, Figure 2 of KIM discloses a display device, comprising
a display panel (AA);
wherein the display panel comprises a hole-punch region (HA, Page 5, English translation), a display region (EA) surrounding the hole-punch region and an isolation region (BA) located between the display region (EA) and the hole-punch region (HA);
wherein the display panel further comprises a base substrate (101), an array layer (112 to 104) and a light-emitting functional layer (130, Page 5, English translation), the array layer and the light-emitting functional layer are sequentially located on a side of the base substrate, wherein the array layer further comprises a first insulating layer (112);
the light-emitting functional layer comprises a cathode (136), and the cathode extends from the display region to the isolation region (BA); and
a groove (110, Page 5, English translation) is provided in the isolation region, and the groove penetrates at least part of the first insulating layer (112);
the groove (110, Page 5, English translation) comprises a first groove division (bottom portion of the groove 110) and a second groove division (upper portion of 110) which are communicated with each other, and the second groove division is located on a side of the first groove division facing away from the base substrate; and
along a direction pointing from the display region to the hole-punch region, a maximum length of the first groove division is greater than a maximum length of the second groove division, and the cathode (136) is disconnected at the groove (110).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-8 and 10-11 are rejected under 35 U.S.C. 103 as being obvious over KIM (KR 20200073550 A) in view of NOH et al (US 20190006521 A1).
Regarding claim 4, Figure 2 of KIM does not explicitly teach display panel according to claim 3, wherein a material of the barrier layer (154, Page 2, English translation) comprises a metal oxide or metal.
However, NOH is a pertinent art which teaches that an active layer of a thin film transistor includes metal oxide ([0103]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use metal oxide in the barrier layer (active layer of a thin film transistor) in the device of KIM according to the teaching of NOH for an improved device with lower cost, since it has been held that choosing from a finite number of identified, predictable solutions such metal oxide in a barrier layer which is an active layer of a thin film transistor, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 5, Figure 2 of KIM discloses that the display panel according to claim 3, wherein the array layer further comprises a first transistor (150, Page 2, English translation), the first transistor comprises a first active layer (154), and the barrier layer and the first active layer are located in a same film layer (based on the Figure 2, 154 is present in 150 and in 110).
KIM does not explicitly teach that a material of the first active layer is a metal oxide and a material of the barrier layer is a metal oxide.
However, NOH is a pertinent art which teaches that an active layer of a thin film transistor includes metal oxide ([0103]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use metal oxide in the barrier layer as well as the active layer of a thin film transistor in the device of KIM according to the teaching of NOH ([0103]) for an improved device with lower cost, since it has been held that choosing from a finite number of identified, predictable solutions such metal oxide in a barrier layer and an active layer of a thin film transistor, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 6, Figure 2 of KIM discloses that the display panel according to claim 5, wherein the array layer further comprises a second insulating layer (116), and along a thickness direction of the base substrate (101), the second insulating layer is located between the barrier layer (154, Page 2, English translation) and the light-emitting functional layer (130); the groove further comprises a third groove division (upper region of 110) communicated with the second groove division, and the third groove division is located on a side of the second groove division (middle region of 110) facing away from the base substrate; and the third groove division penetrates the second insulating layer (116), and a vertical projection of the third groove division on the base substrate covers the vertical projection of the second groove division on the base substrate (101).
Regarding claim 7, Figure 2 of KIM discloses that the display panel according to claim 6, wherein a vertical projection of a side wall of the third groove division (upper region of 110) on the base substrate (101) is located within a vertical projection of the barrier layer (154, Page 2, English translation) on the base substrate.
Regarding claim 8, Figure 2 of KIM does not explicitly teach that the display panel according to claim 6, wherein along the direction pointing from the display region to the hole-punch region, a shortest distance between a side wall of the third groove division and a side wall of the second groove division is d1, wherein d1≥10 μm.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges for an improved device with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Figure 2 of KIM discloses that the display panel according to claim 1, wherein the array layer further comprises a second transistor (150, Page 2, English translation) , the second transistor comprises a second active layer (154), and a material of the second active layer is polycrystalline material; the first insulating layer (considering 112-116 as the first insulating layer) comprises a first insulating sub-layer (112+114) and a second insulating sub-layer (116), and the second insulating sub-layer is located on a side of the first insulating sub-layer facing away from the base substrate; along a thickness direction of the base substrate, the second active layer (154) is located between the first insulating sub-layer and the second insulating sub-layer; and along the thickness direction of the base substrate, a bottom surface of the groove (110) is located on a side of the second insulating sub-layer adjacent to the base substrate.
KIM does not explicitly teach that the second active layer is polycrystalline silicon.
However, NOH is a pertinent art which teaches that an active layer of a thin film transistor includes polycrystalline silicon ([0130]).
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to use polycrystalline silicon the active layer of a thin film transistor in the device of KIM according to the teaching of NOH for an improved device with lower cost, since it has been held that choosing from a finite number of identified, predictable solutions such polycrystalline silicon in an active layer of a thin film transistor, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 11, Figure 2 of KIM discloses that the display panel according to claim 10, wherein along the thickness direction of the base substrate (101), the bottom surface of the groove (110) is located on a side of the base substrate adjacent to the light-emitting functional layer (130, Page 5, English translation).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813