DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 08/18/2026, in which: claim(s) 1 is/are amended; claim(s) 5-6, and 8-14 is/are cancelled; claim(s) 15-29 is/are newly added; and the rejection of the claims are traversed. Claim(s) 1-4, 7, and 15-29 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 08/18/2026, with respect to the rejection(s) of claim(s) 7 under 35 U.S.C. 112(b) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 15-16, 20, 22-23, 25, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20170148811 A1, hereinafter Z1), and further in view of Chen et al. (US 20180247821 A1, hereinafter C1).
Regarding independent claim 1, Z1 discloses in Z1 FIG. 73 and 75B and associated text A memory array comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers (insulating layers 32/132/232 and conductive layers 46/146 laterally spaced apart into vertically stacked memory blocks by separator 78), channel-material strings of memory cells extending through the insulative tiers and the conductive tiers (channels 60 of memory stack structures 55), intervening material being laterally between and longitudinally-along immediately-laterally-adjacent of the memory blocks (source conductive layer 166, which is between and along immediately-laterally-adjacent memory blocks, as shown in Z1 FIG. 75B); the laterally-spaced memory blocks in a lower one of the conductive tiers comprising elemental-form metal (as interpreted, the lower one conductive tier includes at least source connection layer 146, which may comprise an elemental metal (Z1 [0267])) that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks (as shown in Z1 FIG. 75B); a lowest of the conductive tiers being directly below and conductive material thereof being directly against a bottom of the elemental-form metal of the lower one conductive tier (as interpreted, the lowest conductive tier includes at least matrix material layer 138, which is conductive (Z1 [0262]) and directly against a bottom of 146 in the embodiments where optional dielectric etch stop layer 145 is not included), the conductive material of the lowest conductive tier extending laterally outward of the elemental-form metal of the lower one conductive tier in the immediately-laterally-adjacent memory blocks (138 extends outward of 146 in the memory blocks as interpreted, e.g. into the region below 78); and the intervening material extending downwardly into the lowest conductive tier (166 extends downward into 138, as shown). Z1, in the embodiment disclosed in Z1 FIG. 73 and 75B and associated text, does not explicitly disclose a metal silicide or a metal-germanium compound that is directly against laterally-inner sides of the elemental-form metal in the lower one conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower one conductive tier, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal; or metal-compound linings that are individually directly above the conductive material of the lowest conductive tier and directly against laterally-outer sides of the elemental-form metal of the lower one conductive tier of the immediately-laterally-adjacent memory blocks, the metal compound of the metal-compound linings being of different composition from that of the intervening material, the intervening material being laterally between the metal-compound linings and extending downwardly into the lowest conductive tier.
However, Z1 discloses in the embodiment of Z1 FIG. 19 and associated text metal-compound linings that are individually directly above the conductive material of the lowest conductive tier (insulating spacer 74, which can be a dielectric metal oxide (Z1 [0161]), i.e. a metal compound, and is directly above source conductive layer 76L, which is the lowest conductive tier and analogous to matrix material 138 of the embodiment of Z1 FIG. 73), the metal compound of the metal-compound linings being of different composition from that of the intervening material (74 is a dielectric metal oxide (Z1 [0161]), while metallic fill material layer 76B, which is interpreted as the intervening material and is analogous to source conductive layer 166 of the embodiment of Z1 FIG. 73, is e.g., copper (Z1 [0167])), the intervening material being laterally between the metal-compound linings and extending downwardly into the lowest conductive tier (76B is both between 74 and extending into 76L).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 FIG. 73 with the insulating spacers and associated structures of Z1 FIG. 19 such that the spacers are directly against laterally-outer sides of the elemental-form metal of the lower one conductive tier of the immediately-laterally-adjacent memory blocks (since 74 is formed along sidewalls of trench 79, in which the laterally outer sides of the elemental form metal of the lower one conductive tier 146, as interpreted, are exposed) to provide a source contact via structure enabling connection to the common source layer through trench 79.
Additionally, in the same field of endeavor, C1 discloses a metal silicide or a metal-germanium compound that is directly against the elemental-form metal, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal (nucleation layer 16 may be tungsten silicide, and is formed between metal 18, which may be tungsten, and a silicon oxide substrate 12 (C1 [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 with the silicide nucleation layer of C1 to provide a metal silicide between the metal source connection layer 146 and silicon oxide (C1 [0103]) outer blocking dielectric layer 502 (i.e. directly against laterally-inner sides of the elemental-form metal in the lower one conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower one conductive tier) because doing so would improve the nucleation performance of the metal (C1 [0009]).
Regarding dependent claim 2, Z1, as modified by C1, further discloses the memory array of claim 1 comprising the metal silicide (nucleation layer 16 may be tungsten silicide (C1 [0036])).
Regarding independent claim 15, Z1 discloses in Z1 FIG. 73 and 75B and associated text A memory array comprising: a conductor tier comprising conductor material (blanket conductor layer 136 which includes conductive materials (Z1 [0261])); laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers (insulating layers 32/132/232 and conductive layers 46/146 laterally spaced apart into vertically stacked memory blocks by separator 78), channel-material strings of memory cells extending through the insulative tiers and the conductive tiers (channels 60 of memory stack structures 55), intervening material being laterally between and longitudinally-along immediately-laterally-adjacent of the memory blocks (source conductive layer 166, which is between and along immediately-laterally-adjacent memory blocks, as shown in Z1 FIG. 75B); the laterally-spaced memory blocks in a lower one of the conductive tiers comprising elemental-form metal (as interpreted, the lower one conductive tier includes at least source connection layer 146, which may comprise an elemental metal (Z1 [0267])) that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks (as shown in Z1 FIG. 75B); a lowest of the conductive tiers comprising conductive material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier (as interpreted, the lowest conductive tier includes at least matrix material layer 138, which is conductive (Z1 [0262]), and the portions of source conductive layer 166 extending into the tier containing 138, which are electrically coupled to semiconductor channels 60 and blanket conductor layer 136, as shown), the conductive material of the lowest conductive tier being directly below and directly against a bottom of the elemental-form metal of the lower one conductive tier (138 is directly against a bottom of 146 in the embodiments where optional dielectric etch stop layer 145 is not included), the conductive material of the lowest conductive tier extending laterally outward of the elemental-form metal of the lower one conductive tier in the immediately-laterally-adjacent memory blocks (138 extends outward of 146 in the memory blocks as interpreted, e.g. into the region below 78); and the intervening material extending downwardly into the lowest conductive tier (166 extends downward into 138, as shown). Z1, in the embodiment disclosed in Z1 FIG. 73 and 75B and associated text, does not explicitly disclose a metal silicide or a metal-germanium compound that is directly against laterally-inner sides of the elemental-form metal in the lower one conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower one conductive tier, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal; or metal-compound linings that are individually directly above the conductive material of the lowest conductive tier and directly against laterally-outer sides of the elemental-form metal of the lower one conductive tier of the immediately-laterally-adjacent memory blocks, the metal compound of the metal-compound linings being of different composition from that of the intervening material, the intervening material being laterally between the metal-compound linings and extending downwardly into the lowest conductive tier.
However, Z1 discloses in the embodiment of Z1 FIG. 19 and associated text metal-compound linings that are individually directly above the conductive material of the lowest conductive tier (insulating spacer 74, which can be a dielectric metal oxide (Z1 [0161]), i.e. a metal compound, and is directly above source conductive layer 76L, which is the lowest conductive tier and analogous to matrix material 138 of the embodiment of Z1 FIG. 73), the metal compound of the metal-compound linings being of different composition from that of the intervening material (74 is a dielectric metal oxide (Z1 [0161]), while metallic fill material layer 76B, which is interpreted as the intervening material and is analogous to source conductive layer 166 of the embodiment of Z1 FIG. 73, is e.g., copper (Z1 [0167])), the intervening material being laterally between the metal-compound linings and extending downwardly into the lowest conductive tier (76B is both between 74 and extending into 76L).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 FIG. 73 with the insulating spacers and associated structures of Z1 FIG. 19 such that the spacers are directly against laterally-outer sides of the elemental-form metal of the lower one conductive tier of the immediately-laterally-adjacent memory blocks (since 74 is formed along sidewalls of trench 79, in which the laterally outer sides of the elemental form metal of the lower one conductive tier 146, as interpreted, are exposed) to provide a source contact via structure enabling connection to the common source layer through trench 79.
Additionally, in the same field of endeavor, C1 discloses a metal silicide or a metal-germanium compound that is directly against the elemental-form metal, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal (nucleation layer 16 may be tungsten silicide, and is formed between metal 18, which may be tungsten, and a silicon oxide substrate 12 (C1 [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 with the silicide nucleation layer of C1 to provide a metal silicide between the metal source connection layer 146 and silicon oxide (C1 [0103]) outer blocking dielectric layer 502 (i.e. directly against laterally-inner sides of the elemental-form metal in the lower one conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower one conductive tier) because doing so would improve the nucleation performance of the metal (C1 [0009]).
Regarding dependent claim 16, Z1, as modified by C1, further discloses the memory array of claim 15 comprising the metal silicide (nucleation layer 16 may be tungsten silicide (C1 [0036])).
Regarding dependent claim 20, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 1 wherein the metal-compound linings extend vertically upward into the insulative tier that is immediately-above the lowest conductive tier (spacers 74 extend upward to the surface of the device, which, as combined, would include isolation dielectric layer 148, which is interpreted as the insulative tier that is immediately-above the lowest conductive tier).
Regarding dependent claim 22, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 1 wherein the metal-compound linings do not extend laterally outward of the conductive material of the lowest conductive tier (spacers 74 do not extend laterally outward of conductive matrix 138, as combined).
Regarding dependent claim 23, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 22 wherein the metal-compound linings extend vertically upward into the insulative tier that is immediately-above the lowest conductive tier (spacers 74 extend upward to the surface of the device, which, as combined, would include isolation dielectric layer 148, which is interpreted as the insulative tier that is immediately-above the lowest conductive tier).
Regarding dependent claim 25, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 15 wherein the metal-compound linings extend vertically upward into the insulative tier that is immediately-above the lowest conductive tier (spacers 74 extend upward to the surface of the device, which, as combined, would include isolation dielectric layer 148, which is interpreted as the insulative tier that is immediately-above the lowest conductive tier).
Regarding dependent claim 27, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 15 wherein the metal-compound linings do not extend laterally outward of the conductive material of the lowest conductive tier (spacers 74 do not extend laterally outward of conductive matrix 138, as combined).
Regarding dependent claim 28, Z1, as modified by C1, further discloses in Z1 FIG. 19, 73, and 75B and associated text The memory array of claim 27 wherein the metal-compound linings extend vertically upward into the insulative tier that is immediately-above the lowest conductive tier (spacers 74 extend upward to the surface of the device, which, as combined, would include isolation dielectric layer 148, which is interpreted as the insulative tier that is immediately-above the lowest conductive tier).
Claims 3-4 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Z1, and further in view of C1 and Noda et al. (US 20110254122 A1, hereinafter N1).
Regarding dependent claim 3, Z1, as previously modified by C1, discloses the memory array of claim 1. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with germanium forms a metal-germanium compound (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 4, Z1, as previously modified by C1, discloses the memory array of claim 1. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising both silicon and germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with silicon and germanium forms a metal silicide or metal-germanium compound respectively (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide both a metal silicide and a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 17, Z1, as previously modified by C1, discloses the memory array of claim 15. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with germanium forms a metal-germanium compound (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 18, Z1, as previously modified by C1, discloses the memory array of claim 15. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising both silicon and germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with silicon and germanium forms a metal silicide or metal-germanium compound respectively (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide both a metal silicide and a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Z1, and further in view of C1 and Yada et al. (US 20150348984 A1, hereinafter Y1).
Regarding dependent claim 7, Z1, as modified by C1, discloses in Z1 FIG. 73 and associated text The memory array of claim 1 wherein the channel-material strings individually comprise a construction having material radially-outward of the channel material of the channel-material strings and that extends through the insulative tiers and the conductive tiers (memory films 50 are radially outward of channels 60). Z1, as modified by C1, does not explicitly disclose the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions.
However, in the same field of endeavor, Y1 discloses in Y1 FIG. 5D and 7A and associated text the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions (dielectric blocking layer 186 is between both gate electrodes 3 and 127, corresponding to the metal silicide and/or metal-germanium compound, and the outermost elements 9 and 703 of the channel material string construction, laterally spacing the electrodes from the constructions everywhere).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the additionally metal oxide layer Y1, spacing apart the metal silicide and/or metal-germanium compound from channel strings to reduce transistor performance of source connection layer 146 (Y1 [0107]), which one of ordinary skill in the art would recognize as a potentially desirable outcome when, for example, the source connection layer 146 is solely employed to enable electrical contact between the source connection layer 146 and a contact via structure, as it is used in Z1 (Z1 [0267]).
Regarding dependent claim 19, Z1, as modified by C1, discloses in Z1 FIG. 73 and associated text The memory array of claim 15 wherein the channel-material strings individually comprise a construction having material radially-outward of the channel material of the channel-material strings and that extends through the insulative tiers and the conductive tiers (memory films 50 are radially outward of channels 60). Z1, as modified by C1, does not explicitly disclose the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions.
However, in the same field of endeavor, Y1 discloses in Y1 FIG. 5D and 7A and associated text the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions (dielectric blocking layer 186 is between both gate electrodes 3 and 127, corresponding to the metal silicide and/or metal-germanium compound, and the outermost elements 9 and 703 of the channel material string construction, laterally spacing the electrodes from the constructions everywhere).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the additionally metal oxide layer Y1, spacing apart the metal silicide and/or metal-germanium compound from channel strings to reduce transistor performance of source connection layer 146 (Y1 [0107]), which one of ordinary skill in the art would recognize as a potentially desirable outcome when, for example, the source connection layer 146 is solely employed to enable electrical contact between the source connection layer 146 and a contact via structure, as it is used in Z1 (Z1 [0267]).
Allowable Subject Matter
Claims 21, 24, 26, and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claims 21, 24, 26, and 29, the prior art of record to the examiner’s
knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention wherein the metal-compound linings do not extend vertically upward into the conductive tier that is immediately-above the insulative tier that is immediately-above the lowest conductive tier; in combination with the other recited limitations. This structure is not taught or rendered obvious by the prior art of record.
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200127004 A1, pertaining to a memory array having similar structures; and
US 20150001607 A1, pertaining to the use of metal compound spacers to prevent whiskers when etching through elemental metal layers.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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