DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 5-6 and 12-13 are objected to because of the following informalities:
Claims 5-6 and 12-13 are each missing the article “an” in “laterally-outer sides of an individual of the laterally-spaced memory blocks.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 recites the limitation "the channel material". There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner interprets the claim as reciting “a channel material”.
Claim 14 recites the limitation "the channel material". There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner interprets the claim as reciting “a channel material”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 20170148811 A1, hereinafter Z1), and further in view of Chen et al. (US 20180247821 A1, hereinafter C1).
Regarding independent claim 1, Z1 discloses in Z1 FIG. 73 and 75B and associated text A memory array comprising: laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers (insulating layers 32/132/232 and conductive layers 46/146 laterally spaced apart into vertically stacked memory blocks by separator 78), channel-material strings of memory cells extending through the insulative tiers and the conductive tiers (channels 60 of memory stack structures 55); the laterally-spaced memory blocks in a lower one of the conductive tiers comprising elemental-form metal (as interpreted, the lowest conductive tier includes at least source connection layer 146, which may comprise an elemental metal (Z1 [0267])) that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks (as shown in Z1 FIG. 75B). Z1 does not explicitly disclose a metal silicide or a metal-germanium compound that is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal.
However, in the same field of endeavor, C1 discloses a metal silicide or a metal-germanium compound that is directly against the elemental-form metal, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal (nucleation layer 16 may be tungsten silicide, and is formed between metal 18, which may be tungsten, and a silicon oxide substrate 12 (C1 [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 with the silicide nucleation layer of C1 to provide a metal silicide between the metal source connection layer 146 and silicon oxide (C1 [0103]) outer blocking dielectric layer 502 (i.e. directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier) because doing so would improve the nucleation performance of the metal (C1 [0009]).
Regarding dependent claim 2, Z1, as modified by C1, further discloses the memory array of claim 1 comprising the metal silicide (nucleation layer 16 may be tungsten silicide (C1 [0036])).
Regarding dependent claim 5, Z1, as modified by C1, further discloses in Z1 FIG. 73 and associated text The memory array of claim 1 wherein at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks has its laterally-outer side being the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks (source connection layer 146 is at the outer side of at least one memory block as shown).
Regarding independent claim 8, Z1 discloses in Z1 FIG. 73 and 75B and associated text A memory array comprising: a conductor tier comprising conductor material (blanket conductor layer 136 which includes conductive materials (Z1 [0261])); laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier (insulating layers 32/132/232 and conductive layers 46/146 laterally spaced apart into vertically stacked memory blocks by separator 78), channel-material strings of memory cells extending through the insulative tiers and the conductive tiers (channels 60 of memory stack structures 55); a lowest of the conductive tiers comprising conductive material that directly electrically couples together channel material of the channel-material strings and the conductor material of the conductor tier (as interpreted, the lowest conductive tier includes at least source connection layer 146, source conductive layer 166, and matrix material layer 138, of which layers 166 and 138 are both conductive (Z1 [0262] and [0267]) and together connect channel material 60 to the blanket conductor layer 136); an uppermost portion of the conductive material in the lowest conductive tier comprising elemental-form metal (source connection layer 146, which may comprise an elemental metal (Z1 [0267])) that extends longitudinally-along the laterally-spaced memory blocks proximate laterally-outer sides of the laterally-spaced memory blocks in the lowest conductive tier (as shown in Z1 FIG. 75B). Z1 does not explicitly disclose the uppermost portion of the conductive material in the lowest conductive tier comprising a metal silicide or a metal-germanium compound that is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lowest conductive tier, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal.
However, in the same field of endeavor, C1 discloses a metal silicide or a metal-germanium compound that is directly against the elemental-form metal, the metal of the metal silicide or of the metal-germanium compound being the same as that of the elemental-form metal (nucleation layer 16 may be tungsten silicide, and is formed between metal 18, which may be tungsten, and a silicon oxide substrate 12 (C1 [0036])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1 with the silicide nucleation layer of C1 to provide a metal silicide between the metal source connection layer 146 and silicon oxide (C1 [0103]) outer blocking dielectric layer 502 (i.e. directly against laterally-inner sides of the elemental-form metal in the uppermost portion of the conductive material in the lowest conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier) because doing so would improve the nucleation performance of the metal (C1 [0009]).
Regarding dependent claim 9, Z1, as modified by C1, further discloses the memory array of claim 9 comprising the metal silicide (nucleation layer 16 may be tungsten silicide (C1 [0036])).
Regarding dependent claim 12, Z1, as modified by C1, further discloses in Z1 FIG. 73 and associated text The memory array of claim 8 wherein at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks in the uppermost portion has its laterally-outer side being the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks (source connection layer 146 is at the outer side of at least one memory block as shown).
Claims 3-4 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Z1, and further in view of C1 and Noda et al. (US 20110254122 A1, hereinafter N1).
Regarding dependent claim 3, Z1, as previously modified by C1, discloses the memory array of claim 1. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with germanium forms a metal-germanium compound (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 4, Z1, as previously modified by C1, discloses the memory array of claim 1. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising both silicon and germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with silicon and germanium forms a metal silicide or metal-germanium compound respectively (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide both a metal silicide and a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 10, Z1, as previously modified by C1, discloses the memory array of claim 8. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with germanium forms a metal-germanium compound (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Regarding dependent claim 11, Z1, as previously modified by C1, discloses the memory array of claim 8. Z1, as previously modified by C1, does not explicitly disclose comprising the metal-germanium compound.
However, C1 discloses that in some embodiments nucleation layer 16 may be replaced by a doped amorphous silicon layer comprising both silicon and germanium (C1 [0060] and [0067]).
Additionally, in the same field of endeavor, N1 discloses reacting a metal with silicon and germanium forms a metal silicide or metal-germanium compound respectively (N1 [0066]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as previously modified by C1, with the reaction of metal with a germanium-containing semiconductor (replacing and performing the same function as nucleation layer 16, as taught by C1) of N1 to provide both a metal silicide and a metal-germanium compound in the source connection layer 146 because said the resulting compound reaction would provide the layer with reduced resistance compared to semiconductor material (N1 [0066]), improving the efficiency of the memory array.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Z1, and further in view of C1 and Lee et al. (US 20150001607 A1, hereinafter L1).
Regarding dependent claim 6, Z1, as modified by C1, discloses the memory array of claim 1. Z1, as modified by C1, does not explicitly disclose at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks has its laterally-outer side being a metal compound that extends longitudinally-along the laterally-spaced memory blocks in the one lower tier, the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks being directly against the metal compound laterally-inward thereof in the one lower tier.
However, in the same field of endeavor, L1 discloses in L1 FIG. 10, 12, and 13 and associated text at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks has its laterally-outer side being a metal compound (spacers 352 may be one of a variety of metal compounds (L1 [0042] and [0050]) and are formed on the outer sidewalls of metal control gates 336, which correspond to an elemental-form metal) that extends longitudinally-along the laterally-spaced memory blocks, the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks being directly against the metal compound laterally-inward thereof (the aforementioned structure being best shown in L1 FIG. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the metal compound spacer of L1 on outer sidewalls of source connection line 146 (in the one lower tier) to prevent or reduce amount of at least one of tungsten oxide whiskers, tungsten surface diffusion and etch byproduct generated during the stack etching (L1 [0027]).
Regarding dependent claim 13, Z1, as modified by C1, discloses the memory array of claim 8. Z1, as modified by C1, does not explicitly disclose at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks in the uppermost portion has its laterally-outer side being a metal compound, the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks being directly against the metal compound laterally-inward thereof.
However, in the same field of endeavor, L1 discloses in L1 FIG. 10, 12, and 13 and associated text at least one of the laterally-outer sides of an individual of the laterally-spaced memory blocks has its laterally-outer side being a metal compound (spacers 352 may be one of a variety of metal compounds (L1 [0042] and [0050]) and are formed on the outer sidewalls of metal control gates 336, which correspond to an elemental-form metal), the elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks being directly against the metal compound laterally-inward thereof (the aforementioned structure being best shown in L1 FIG. 13).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the metal compound spacer of L1 on outer sidewalls of source connection line 146 (in the uppermost portion) to prevent or reduce amount of at least one of tungsten oxide whiskers, tungsten surface diffusion and etch byproduct generated during the stack etching (L1 [0027]).
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Z1, and further in view of C1 and Yada et al. (US 20150348984 A1, hereinafter Y1).
Regarding dependent claim 7, Z1, as modified by C1, discloses in Z1 FIG. 73 and associated text The memory array of claim 1 wherein the channel-material strings individually comprise a construction having material radially-outward of a channel material of the channel-material strings and that extends through the insulative tiers and the conductive tiers (memory films 50 are radially outward of channels 60). Z1, as modified by C1, does not explicitly disclose the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions.
However, in the same field of endeavor, Y1 discloses in Y1 FIG. 5D and 7A and associated text the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions (dielectric blocking layer 186 is between both gate electrodes 3 and 127, corresponding to the metal silicide and/or metal-germanium compound, and the outermost elements 9 and 703 of the channel material string construction, laterally spacing the electrodes from the constructions everywhere).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the additionally metal oxide layer Y1, spacing apart the metal silicide and/or metal-germanium compound from channel strings to reduce transistor performance of source connection layer 146 (Y1 [0107]), which one of ordinary skill in the art would recognize as a potentially desirable outcome when, for example, the source connection layer 146 is solely employed to enable electrical contact between the source connection layer 146 and a contact via structure, as it is used in Z1 (Z1 [0267]).
Regarding dependent claim 14, Z1, as modified by C1, discloses in Z1 FIG. 73 and associated text The memory array of claim 8 wherein the channel-material strings individually comprise a construction having material radially-outward of a channel material of the channel-material strings and that extends through the insulative tiers and the conductive tiers (memory films 50 are radially outward of channels 60). Z1, as modified by C1, does not explicitly disclose the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions.
However, in the same field of endeavor, Y1 discloses in Y1 FIG. 5D and 7A and associated text the metal silicide or the metal-germanium compound being everywhere laterally-spaced from said constructions (dielectric blocking layer 186 is between both gate electrodes 3 and 127, corresponding to the metal silicide and/or metal-germanium compound, and the outermost elements 9 and 703 of the channel material string construction, laterally spacing the electrodes from the constructions everywhere).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the memory array of Z1, as modified by C1, with the additionally metal oxide layer Y1, spacing apart the metal silicide and/or metal-germanium compound from channel strings to reduce transistor performance of source connection layer 146 (Y1 [0107]), which one of ordinary skill in the art would recognize as a potentially desirable outcome when, for example, the source connection layer 146 is solely employed to enable electrical contact between the source connection layer 146 and a contact via structure, as it is used in Z1 (Z1 [0267]).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20200127004 A1, pertaining to a memory array having similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights