DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, drawn to claims 1-12, in the reply filed on 8/20/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the side surface including: a first side surface in contact with the second electrode; an upper surface overlapping a portion of the first electrode; and a second side surface spaced apart from the first side surface." in lines 14-18 in the claim. However, it’s contradictory to have an upper surface be a part of a side surface. An upper surface is usually a lateral surface, and a side surface is usually a vertical surface and so it is indefinite to have one be part of the other. For examination purposes, the upper surface can be considered as an upper surface of a portion of the intermediate layer.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jin et al. (Pub. No. US 20160027857 A1), hereinafter as Jin.
PNG
media_image1.png
486
587
media_image1.png
Greyscale
Image A: close up of Jin Fig. 2, showcasing intermediate insulating layer and inter-insulating layer.
PNG
media_image2.png
435
492
media_image2.png
Greyscale
Image B: close up of Jin Fig. 2, showcasing groove and side surface.
PNG
media_image3.png
478
648
media_image3.png
Greyscale
Image C: close up of Jin Fig. 2, showcasing various surfaces and portion of first electrode.
With regards to claim 1, A display panel, comprising: a base layer (see Jin Fig. 2, substrate SUB; Jin [0046]); a transistor (see Jin Fig. 2, thin film transistor T; Jin [0046]) disposed on the base layer (see Jin Fig. 2), and including a semiconductor pattern (see Jin Fig. 2, active layer 210; Jin [0048]), a gate (see Jin Fig. 2, gate electrode 230; Jin [0051]) overlapping the semiconductor pattern (see Jin Fig. 2), and a source (see Jin Fig. 2, source electrode 250; Jin [0049]) and a drain (see Jin Fig. 2, drain electrode 270; Jin [0049]) connected to the semiconductor pattern (see Jin Fig. 2); a light-emitting element (see Jin Fig. 2, light emitting element EL; Jin [0040]) connected to the transistor (see Jin [0046]: “The thin film transistor T may be one of the first and second switching devices T1 and T2 shown in FIG. 1.”, where the second switching device T2 is connected to the light emitting element EL as seen in Jin Fig. 1.); a capacitor (see Jin Fig. 2, capacitor C; Jin [0046]) including a first electrode (see Jin Fig. 2, first electrode 110; Jin [0047]) disposed in a same layer as the semiconductor pattern (see Jin Fig. 2 and Jin [0048]: “The first electrode 110 of the capacitor C is located at the same layer level as that of an active layer 210 of the thin film transistor T.”), and a second electrode (see Jin Fig. 2, second electrode 130; Jin [0047]) disposed on the first electrode (see Jin Fig. 2); an inter-insulating layer (see Jin Fig. 2, first insulating layer 13; Jin [0053]) disposed between the semiconductor pattern and the gate (see Jin Fig. 2); and an intermediate insulating layer (see Jin Fig. 2 and Image A, second insulating layer 15; Jin [0049]) disposed between the gate and the source and the gate and the drain (see Jin Fig. 2), the intermediate insulating layer including: a side surface (see Image B) in which a groove (see Image B) which exposes the second electrode is defined (see Image C and Jin Fig. 2), the side surface including: a first side surface (see Image C) in contact with the second electrode (see Image C); an upper surface (see Image C) overlapping a portion (see Image C) of the first electrode (see Image C); and a second side surface (see Image C) spaced apart from the first side surface (see Image C).
With regards to claim 2, Jin teaches the display panel of claim 1, wherein the inter-insulating layer (see Jin Fig. 2, first insulating layer 13) and the intermediate insulating layer (see Jin Fig. 2, second insulating layer 15) are disposed on the portion (see Image C) of the first electrode (see Jin Fig. 2, first electrode 110), and the portion of the first electrode does not overlap the second electrode (see Jin Fig. 2, second electrode 130).
With regards to claim 3, Jin teaches the display panel of claim 1, wherein the source (see Jin Fig. 2, source electrode 250) and the drain (see Jin Fig. 2, drain electrode 270) contact the semiconductor pattern (see Jin Fig. 2, active layer 210) through contact holes (see Jin Fig. 8, contact holes H1 and H2; Jin [0085]) which penetrate the inter-insulating layer (see Jin Fig. 2, first insulating layer 13) and the intermediate insulating layer (see Jin Fig. 2 and Image A, second insulating layer 15).
With regards to claim 4, Jin teaches the display panel of claim 1, wherein the gate (see Jin Fig. 2, gate electrode 230) and the second electrode (see Jin Fig. 2, second electrode 130) are disposed on the inter-insulating layer (see Jin Fig. 2, first insulating layer 13), and a first thickness (see Jin Fig. 2, second thickness D2; Jin [0050]) of the second electrode is smaller than a second thickness (see Jin Fig. 2, thickness D1; and see Jin [0051]: “The first thickness D1 of the second region 130b of the second electrode 130 is the same as a thickness D1 of the gate electrode 230.”) of the gate (see Jin [0051]: “The second thickness D2 of the first region 130a of the second electrode 130 is less than the first thickness D1.”).
With regards to claim 6, Jin teaches the display panel of claim 1, further comprising a lower insulating layer (see Jin Fig. 2, buffer layer 11; Jin [0046]) which is disposed on the base layer (see Jin Fig. 2, substrate SUB) and on which the first electrode (see Jin Fig. 2, first electrode 110) and the semiconductor pattern (see Jin Fig. 2, active layer 210) are disposed (see Jin Fig. 2), and an upper insulating layer (see Jin Fig. 2, third insulating layer 17; Jin [0052]) which is disposed on the intermediate insulating layer (see Jin Fig. 2 and Image A, second insulating layer 15) and covers the source (see Jin Fig. 2, source electrode 250) and the drain (see Jin Fig. 2, drain electrode 270).
With regards to claim 7, Jin teaches the display panel of claim 6, wherein the upper insulating layer (see Jin Fig. 2, third insulating layer 17) is disposed in the groove (see Image B) and in contact with the second electrode (see Jin Fig. 2, second electrode 130).
With regards to claim 9, Jin teaches the display panel of claim 1, wherein the first electrode (see Jin Fig. 2, first electrode 110) comprises polysilicon (see Jin [0070]: “… the semiconductor layer is patterned (etched) in order to form a first semiconductor layer portion for forming the active layer 210 of the thin film transistor T and a second semiconductor layer portion form forming the first electrode 110 of the capacitor C.”; and see Jin [0073]: “The semiconductor layer may be formed of amorphous silicon or polysilicon.”, where one would choose polysilicon.) and the second electrode (see Jin Fig. 2, second electrode 130) comprises molybdenum (see Jin [0051]: “The second electrode 130 of the capacitor C may be formed of the same material as that of the gate electrode 230.”; and see Jin [0057]: “The gate electrode 230 may be formed to have a single-layered structure or a multi-layered structure by using one or more metal materials selected from aluminum (Al), …, molybdenum (Mo), …” where one would choose molybdenum.).
With regards to claim 11, Jin teaches the display panel of claim 9, wherein the semiconductor pattern (see Jin Fig. 2, active layer 210) comprises polysilicon (see Jin [0070]: “… the semiconductor layer is patterned (etched) in order to form a first semiconductor layer portion for forming the active layer 210 of the thin film transistor T and a second semiconductor layer portion form forming the first electrode 110 of the capacitor C.”; and see Jin [0073]: “The semiconductor layer may be formed of amorphous silicon or polysilicon.”, where one would choose polysilicon.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jin, in view of Kwon et al. (Pub. No.: US 20110079786 A1), hereinafter as Kwon.
[Cao et al. (‘Boron Doping in Next-Generation Materials for Semiconductor Device’), hereinafter as Cao, is used herein as evidence.]
With regards to claim 5, Jin teaches the display panel of claim 4.
Jin does not teach that a difference between the second thickness and the first thickness ranges from about 400 angstroms to about 700 angstroms.
Kwon teaches that a difference between a second thickness (see Kwon Fig. 11, thickness t1; Kwon [0087]) of a gate (see Kwon Fig. 3, gate electrode 155; Kwon [0057]) and a first thickness (see Kwon Fig. 11, thickness t2; Kwon [0087]) of a second electrode (see Kwon Fig. 3, second capacitor electrode 158; Kwon [0057]) ranges from about 400 angstroms to about 700 angstroms (see Kwon [0087]: “The second capacitor electrode 158 may have a thickness t2, e.g., of about 10 nm to about 140 nm, and the gate electrode 155 may have a thickness t1, e.g., of about 170 nm or more. The thickness t2 of the second capacitor electrode 158 may be about 75% or less of the thickness t1 of the gate electrode 155.” If one chose t1 to be 170nm, then t2 would be about 127.5 nm (75% of 170nm), and the difference between the two thicknesses would be 42.5 nm or 425 angstroms, which falls within the range of 400-700 angstroms.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the first and second thicknesses of Jin with the thicknesses taught by Kwon in order to prevent doping into the transistor’s channel area while allowing the first electrode to be doped (see Kwon [0059]: “That is, a gate electrode 155 with a thickness of about 170 nm or higher may have sufficient thickness to prevent or substantially minimize impurity doping into the channel region 1355 of the semiconductor layer 135 during manufacturing.”).
With regards to claim 10, Jin teaches the display panel of claim 9.
Jin does not teach that the polysilicon is impregnated with boron.
Kwon teaches that a first electrode (see Kwon Fig. 3, first capacitor electrode 138; Kwon [0053]) comprises polysilicon (see Kwon [0010]: “The first capacitor electrode and the semiconductor layer may each include an impurity-doped polycrystalline silicon layer,”), wherein the polysilicon is impregnated with boron (see Kwon [0013]: “The impurity doped at the first capacitor electrode and the semiconductor layer respectively may include an impurity selected from a P-type impurity and an N-type impurity. The impurity may include boron.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to dope the polysilicon of Jin with the boron taught by Kwon because boron has good diffusivity (see Cao pg. 2: “Boron is one of the essential dopants for shallow doping in silicon because of its good diffusivity [3].”).
Claims 8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jin, in view of Noh et al. (Pub. No.: US 20230207570 A1), hereinafter as Noh.
PNG
media_image4.png
397
462
media_image4.png
Greyscale
Image D: closeup of Noh Fig. 2, showcasing a contact hole.
With regards to claim 8, Jin teaches the display panel of claim 1, further comprising an upper insulating layer (see Jin Fig. 2, third insulating layer 17; Jin [0052]), wherein the light-emitting element (see Jin Fig. 2, light emitting element EL) comprises an anode (see Jin Fig. 2, pixel electrode 310; and see Jin [0063]: “[0063] The light emitting element EL may be an OLED that includes a pixel electrode (anode electrode) 310, an opposite electrode (cathode electrode) 350 facing the pixel electrode 310, and an organic emission layer 330 located between the pixel electrode 310 and the opposite electrode 350.”) connected to the transistor (see Jin [0046]: “The thin film transistor T may be one of the first and second switching devices T1 and T2 shown in FIG. 1.”, where the second switching device T2 is connected to the light emitting element EL as seen in Jin Fig. 1.), a cathode (see Jin Fig. 2, opposite electrode 350; and see Jin [0063]) disposed on the anode (see Jin Fig. 2), and a light-emitting layer (see Jin Fig. 2, organic emission layer 330; Jin [0063]) disposed between the anode and the cathode (see Jin Fig. 2).
Jin does not teach that the anode is connected to the transistor through a contact hole which penetrates the upper insulating layer.
Noh teaches that an anode (see Noh Fig. 2, first electrode 510; Noh [0057]) is connected to a transistor (see Noh Fig. 2, second thin-film transistor 300; Noh [0030]) through a contact hole (see Image D) which penetrates an upper insulating layer (see Noh Fig. 2, lower protective film 120; Noh [0054]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add a contact hole as taught by Noh to the device of Jin in order to effectively connect the transistor to the light emitting element and allow the transistor to control the light emitting element.
With regards to claim 12, Jin teaches the display panel of claim 1.
Jin does not teach that the display panel further comprises a thin-film encapsulation layer which covers the light-emitting element.
Noh teaches that a display panel further comprises a thin-film encapsulation layer (see Noh Fig. 2, encapsulating element 600; Noh [0065]) which covers a light-emitting element (see Noh Fig. 2, light-emitting device 500; Noh [0057]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add the thin-film encapsulation layer taught by Noh to the device of Jin in order to protect the light emitting element (see Noh [0065]: “The encapsulating element 600 may prevent the damage of the light-emitting devices 500 due to external impact or moisture.”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EKATERINA T BIRCH whose telephone number is (571)272-8676. The examiner can normally be reached Mon-Fri, 8am-4pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at 5712721657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.T.B./Examiner, Art Unit 2818
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
Prosecution Insights