DETAILED ACTION
This correspondence is in response to the communications received July 15, 2026. Claims 1-9 and 11-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restriction
Applicant’s election without traverse of Species I in the reply filed on July 15, 2026 is acknowledged. Claim 10 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 15, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 19, and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The recitation, “in contact with an upper surface of the first etching stop layer on the upper surface of the first etching stop layer” renders the claim indefinite, as it is unclear which two etch stop layers are being referred to, or if this is a mistake of redundancy.
Relevant Prior Art
Lanzillo et al. (US 2023/0144842) Fig. 2A, shown below.
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More et al. (US 2022/0216102) Fig. 3B, shown below. Cobalt cap details, ¶ 0032-0034, 0065 and 0066.
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Yi et al. (US 2022/0122915) Fig. 4, shown below.
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Hsieh et al. (US 2021/0202310) Fig. 13 and 18, shown below. ¶ 0044, capping layer is cobalt.
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Xu et al. (US 2021/0062330) Fig. 2E, shown below.
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Chen et al. (US 2020/0321247) Fig. 2E, shown below.
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Naik et al. (US 11,373,903) Fig. 2D, shown below.
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Chi et al. (US 9,487,864) Fig. 2C, shown below.
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Edelstein et al. (US 9,455,182) Fig. 2, shown below.
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Briggs et al. (US 9,780,035) discusses hexagonal close packed cobalt, col. 2, line 66 to col. 3, line 8.
Wu et al. (US 2023/0377966) Fig. 12A, shown below.
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Hsieh et al. (US 2022/0367265) Fig. 18, shown below.
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Lin et al. (US 2018/0261537) Fig. 6, shown below. Etch stop interacts with Cobalt cap layer as prior art evidence directed to Species I.
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Shih et al. (US 2007/0048991) Fig. 1H, shown below.
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Park et al. (US 2006/0216929) Fig. 1F, shown below.
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Lin et al. (US 2024/0258160) Fig. 13, shown below.
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 1 and 2, a semiconductor device comprising:
a substrate (100);
an interlayer insulating layer (130) disposed on the substrate (on 100);
an upper wiring trench (150T) disposed in the interlayer insulating layer (in 130); and
an upper wiring layer comprising:
an upper wiring barrier layer (151, ¶ 0046) disposed along a sidewall and a bottom surface of the upper wiring trench (151 in 150T),
an upper wiring filling layer (152, ¶ 0049) disposed on the upper wiring barrier layer (152 on 151) so as to fill at least a portion of an inside of the upper wiring trench (152 fills most of 150T), and
an upper wiring capping layer (153) disposed on an upper surface of the upper wiring filling layer (on 152),
wherein the upper wiring capping layer includes cobalt (Co), and
wherein a volume percentage of a crystal structure having a hexagonal close-packed structure in the upper wiring capping layer is in a range of about 80% to about 100% (discussed in ¶ 0051).
9. The semiconductor device of claim 1, wherein a first vertical level of an upper surface of the upper wiring capping layer is higher than a second vertical level of an upper surface of the interlayer insulating layer. [directed to first species]
10. The semiconductor device of claim 1, wherein a sidewall of the upper wiring capping layer is in contact with the upper wiring barrier layer. [directed to second species]
11. A semiconductor device comprising:
a substrate;
an interlayer insulating layer disposed on the substrate;
a via trench disposed inside the interlayer insulating layer;
a via comprising a via barrier layer disposed along a sidewall and a bottom surface of the via trench,
a via filling layer disposed on the via barrier layer so as to fill an inside of the via trench;
an upper wiring trench disposed on the via trench in the interlayer insulating layer; and
an upper wiring layer comprising an upper wiring barrier layer disposed along a sidewall and a bottom surface of the upper wiring trench,
an upper wiring filling layer disposed on the upper wiring barrier layer so as to fill at least a portion of an inside of the upper wiring trench, and
an upper wiring capping layer disposed on an upper surface of the upper wiring filling layer,
wherein a first width in a horizontal direction of the via is smaller than a second width in the horizontal direction of the upper wiring layer, and
wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.
17. A semiconductor device comprising:
a substrate;
an interlayer insulating layer disposed on the substrate;
an upper wiring trench disposed in the interlayer insulating layer;
an upper wiring layer comprising an upper wiring barrier layer disposed along a sidewall and a bottom surface of the upper wiring trench,
an upper wiring filling layer disposed on the upper wiring barrier layer so as to fill at least a portion of an inside of the upper wiring trench,
an upper wiring capping layer disposed on an upper surface of the upper wiring filling layer; and
a first etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer and the upper wiring capping layer,
wherein a first vertical level of the upper surface of the upper wiring capping layer is higher than a second vertical level of the upper surface of the interlayer insulating layer,
wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.
18. The semiconductor device of claim 17, wherein the first etching stop layer is in contact with a sidewall of the upper wiring capping layer. [directed to first species]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 11, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Griggio et al. (US 2019/0304918).
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[Interpretation #1] Regarding claim 1, the prior art of Chin discloses in Figs. 2-4G, a semiconductor device (see title, “Semiconductor Devices …”) comprising:
a substrate (“substrate 202”, ¶ 0066, shown in Fig. 2);
an interlayer insulating layer (Interpreted to be insulator portions 220, 222, 224, 226, of, “ESL 208, 212, 216, 220, and/or 224, and/or another dielectric layer 206, 210, 214, 222, and/or 226”, ¶ 0074, hereinafter referred to as ‘IIL’) disposed on the substrate (on 202);
an upper wiring trench (Interpreted to be “opening 402 … opening 406”, ¶ 0088, as can be seen in Fig. 4A) disposed in the interlayer insulating layer (in IIL); and
an upper wiring layer (Generally speaking, “BEOL layer 302 includes a dual damascene structure that includes a metallization layer 304 and a via 306 below the metallization layer 304”, ¶ 0072, which specifically are the collection of components of 316, 320 and 322, hereinafter referred to as ‘UWL’) comprising:
an upper wiring barrier layer (“barrier layer 316”, ¶ 0078) disposed along a sidewall and a bottom surface of the upper wiring trench (316 formed on sidewalls and bottom surfaces of 402/406, in Fig. 4C),
an upper wiring filling layer (“conductive structure 320”, ¶ 0083) disposed on the upper wiring barrier layer (on 316) so as to fill at least a portion of an inside of the upper wiring trench (320 fills 402/406, as shown initially in Fig. 4F), and
an upper wiring capping layer (“cobalt (Co) capping layer 322”, ¶ 0083, see Figs. 3 and 4G) disposed on an upper surface of the upper wiring filling layer (322 on upper surface of 320),
wherein the upper wiring capping layer includes cobalt (Co) (“cobalt (Co) capping layer 322”, ¶ 0083).
[Interpretation #2] Regarding claim 1, the prior art of Chin discloses in Figs. 2-4G, a semiconductor device (see title, “Semiconductor Devices …”) comprising:
a substrate (“substrate 202”, ¶ 0066, shown in Fig. 2);
an interlayer insulating layer (Interpreted to be insulator portions 220, 222, 224, 226, of, “ESL 208, 212, 216, 220, and/or 224, and/or another dielectric layer 206, 210, 214, 222, and/or 226”, ¶ 0074, hereinafter referred to as ‘IIL’) disposed on the substrate (on 202);
an upper wiring trench (Interpreted to be “opening 402”, ¶ 0088, as can be seen in Fig. 4A) disposed in the interlayer insulating layer (in IIL); and
an upper wiring layer (portion 304 of, “BEOL layer 302 includes a dual damascene structure that includes a metallization layer 304 and a via 306 below the metallization layer 304”, ¶ 0072, which specifically is the portion of elements of 316, 320 and 322, located in 402, hereinafter referred to as ‘UWL’) comprising:
an upper wiring barrier layer (portion of “barrier layer 316”, ¶ 0078, in 402) disposed along a sidewall and a bottom surface of the upper wiring trench (316 formed on sidewalls and bottom surfaces of 402, in Fig. 4C),
an upper wiring filling layer (portion of “conductive structure 320”, ¶ 0083, in 402) disposed on the upper wiring barrier layer (on 316) so as to fill at least a portion of an inside of the upper wiring trench (320 fills 402, as shown initially in Fig. 4F), and
an upper wiring capping layer (“cobalt (Co) capping layer 322”, ¶ 0083, see Figs. 3 and 4G) disposed on an upper surface of the upper wiring filling layer (322 on upper surface of 320),
wherein the upper wiring capping layer includes cobalt (Co) (“cobalt (Co) capping layer 322”, ¶ 0083).
Chin does not specify, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure in the upper wiring capping layer is in a range of about 80% to about 100%.”
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Griggio discloses in Fig. 3, wherein the “cap 360”, ¶ 0026 is a cobalt cap which is “hexagonal close packed”, see ¶ 0015, “For example, the liner and cap metals can have the same crystal structure, such as molybdenum, tantalum, and tungsten (for body centered cubic metals), or rhodium, palladium, platinum, and gold (for face centered cubic metals), or scandium, titanium, cobalt, technetium, ruthenium, cadmium, rhenium, and osmium (for hexagonal close-packed metals).” Therefore, Griggio’s disclosure satisfies, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure in the upper wiring capping layer is in a range of about 80% to about 100%.” The percentage being fully of the variety disclosed, as no evidence is present to the contrary.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure in the upper wiring capping layer is in a range of about 80% to about 100%.”, as disclosed by Griggio in the system of Chin, for the purpose of reducing the electromigration effects of copper in the electrical connection system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Chin et al. disclose the semiconductor device of claim 1 [Interpretation #2], and Chin discloses further in Figs. 2-4G, comprising:
a via trench (“via opening 406”, ¶ 0087) disposed under the upper wiring trench (under UWT in 402) inside the interlayer insulating layer (in previously identified IIL); and
a via (portions of 316 and 320 specifically within 406) connected to the upper wiring layer (connected to UWT in 402),
the via comprising a via barrier layer (portion of “barrier layer 316”, ¶ 0089, in 406, Fig. 4C) disposed along a sidewall and a bottom surface of the via trench (along sidewalls and bottom surface of 406), and
a via filling layer (portion of “conductive structure 320”, ¶ 0083, in 406, Fig. 4F) disposed on the via barrier layer (320 on 316 in 406) so as to fill an inside of the via trench (320 fills remaining space in 406 after formation of 316),
wherein a first width in a horizontal direction of the via (406) is smaller than a second width in the horizontal direction of the upper wiring layer (406 width smaller than width of 402, see Fig. 4A).
Regarding claim 11, the prior art of Chin discloses in Figs. 2-4G, a semiconductor device (see title, “Semiconductor Devices …”) comprising:
a substrate (“substrate 202”, ¶ 0066, shown in Fig. 2);
an interlayer insulating layer (Interpreted to be insulator portions 220, 222, 224, 226, of, “ESL 208, 212, 216, 220, and/or 224, and/or another dielectric layer 206, 210, 214, 222, and/or 226”, ¶ 0074, hereinafter referred to as ‘IIL’) disposed on the substrate (on 202);
a via trench (“via opening 406”, ¶ 0087, Fig. 4A) disposed inside the interlayer insulating layer (406 in IIL);
a via (portions of 316 and 320 specifically within 406) comprising a via barrier layer (portion of “barrier layer 316”, ¶ 0089, in 406, Fig. 4C) disposed along a sidewall and a bottom surface of the via trench (along sidewalls and bottom surface of 406),
a via filling layer (portion of “conductive structure 320”, ¶ 0083, in 406, Fig. 4F) disposed on the via barrier layer (on 316) so as to fill an inside of the via trench (320 fills remaining space in 406 after formation of 316);
an upper wiring trench (Interpreted to be “opening 402”, ¶ 0088, as can be seen in Fig. 4A) disposed on the via trench (402 on 406) in the interlayer insulating layer (in IIL); and
an upper wiring layer (portions of 316 and 320 specifically within 402) comprising an upper wiring barrier layer (portion of “barrier layer 316”, ¶ 0089, in 402, Fig. 4C) disposed along a sidewall and a bottom surface of the upper wiring trench (along sidewalls and bottom surface of 402),
an upper wiring filling layer (portion of “conductive structure 320”, ¶ 0083, in 402, Fig. 4F) disposed on the upper wiring barrier layer (on 316 in 402) so as to fill at least a portion of an inside of the upper wiring trench (320 fills remaining space in 402 after formation of 316), and
an upper wiring capping layer (“a cobalt (Co) capping layer 322”, ¶ 0083, Fig. 4G) disposed on an upper surface of the upper wiring filling layer (322 on upper surface of 320),
wherein a first width in a horizontal direction of the via (406) is smaller than a second width in the horizontal direction of the upper wiring layer (406 width smaller than width of 402, see Fig. 4A).
Chin does not specify, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.”
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Griggio discloses in Fig. 3, wherein the “cap 360”, ¶ 0026 is a cobalt cap which is “hexagonal close packed”, see ¶ 0015, “For example, the liner and cap metals can have the same crystal structure, such as molybdenum, tantalum, and tungsten (for body centered cubic metals), or rhodium, palladium, platinum, and gold (for face centered cubic metals), or scandium, titanium, cobalt, technetium, ruthenium, cadmium, rhenium, and osmium (for hexagonal close-packed metals).” Therefore, Griggio’s disclosure satisfies, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.” The percentage being fully of the variety disclosed, as no evidence is present to the contrary.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.”, as disclosed by Griggio in the system of Chin, for the purpose of reducing the electromigration effects of copper in the electrical connection system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 12, the prior art of Chin et al. disclose the semiconductor device of claim 11, and Chin discloses, wherein the upper wiring capping layer contains cobalt (Co) (“a cobalt (Co) capping layer 322”, ¶ 0083, Fig. 4G).
Regarding claim 16, the prior art of Chin et al. disclose the semiconductor device of claim 11, and Chin discloses, further comprising:
a lower interlayer insulating layer (“a dielectric layer 218”, ¶ 0065) disposed between an upper surface of the substrate (upper surface of (“substrate 202”, ¶ 0066) and a lower surface of the interlayer insulating layer (lower surface of IIL); and
a lower wiring layer (“conductive structures 244”, ¶ 0070) disposed inside the lower interlayer insulating layer (244 is formed within 218), wherein the lower wiring layer is connected to the via (244 is connected with portions of 316 and 320 specifically within 406)).
Claims 2, 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Griggio et al. (US 2019/0304918) in view of Huang et al. (US 2004/0251549).
Regarding claim 2, the prior art of Chin et al. disclose the semiconductor device of claim 1, however, as Chin does not disclose the details of further upper metallization level constructions, Chin does not disclose, “further comprising a first etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer, or the upper wiring capping layer.”
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It should be noted that UWL/302 of Chin in Fig. 3 is equivalent to metal 252 and via 248 in dielectrics 220, 222, 224 and 226 in Chin Fig. 2. These are understood to be equivalent to the “third metal layer”. Where “first metal layer” is at the device contact level. The “second metal layer” is the via 238 plus wiring 244. The third metal layer is via 248 plus wiring 252. So UWL/302 of Chin has been established as the “third metal layer”, see above Fig. 2.
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Huang discloses in Fig. 1, wherein the equivalent “third metal layer” are the via plus wiring of 42, see “FIG. 1, metal layers one through eight (i.e., layers 32, 38, 42, 50, 56, 62, 68, and 74)”, ¶ 0022. On this third metal layer 42, there is shown an etch stop layer 48, “shown in FIG. 1 are etch stop layers 46, 48 and 54, which are used to protect the dielectric layers 40, 44 and 52, respectively, during etching of trenches in the subsequently formed dielectric layers 44, 52 and 58, respectively”, ¶ 0019. The etch stop layer is formed on the entirety of the below layers, which would then satisfy, “further comprising a first etching stop layer (48, ¶ 0019) disposed on an upper surface of at least one of the interlayer insulating layer (44, ¶ 0019), the upper wiring barrier layer (top surface of 42, ¶ 0019), or the upper wiring capping layer (the cap would be combined into the feature of 42, as has already been disclosed in the rejection of claim 1).”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “further comprising a first etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer, or the upper wiring capping layer”, as disclosed by Huang in the system of Chin, for the purpose of protecting the lower dielectric layers during etching of the trenches used to form the wiring structures. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 5, the prior art of Chin et al. disclose the semiconductor device of claim 2, and in Fig. 1 of Huang, it is disclosed, further comprising an upper interlayer insulating layer (portion 52 of “the dielectric layers 40, 44 and 52”, ¶ 0019) in contact with an upper surface of the first etching stop layer on the upper surface of the first etching stop layer (52 in contact with upper surface of portion 48 of “etch stop layers 46, 48 and 54”, ¶ 0019).
Regarding claim 13, the prior art of Chin et al. disclose the semiconductor device of claim 11, however, as Chin does not disclose the details of further upper metallization level constructions, Chin does not disclose, “further comprising an etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer and the upper wiring capping layer.”
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It should be noted that UWL/302 of Chin in Fig. 3 is equivalent to metal 252 and via 248 in dielectrics 220, 222, 224 and 226 in Chin Fig. 2. These are understood to be equivalent to the “third metal layer”. Where “first metal layer” is at the device contact level. The “second metal layer” is the via 238 plus wiring 244. The third metal layer is via 248 plus wiring 252. So UWL/302 of Chin has been established as the “third metal layer”, see above Fig. 2.
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Huang discloses in Fig. 1, wherein the equivalent “third metal layer” are the via plus wiring of 42, see “FIG. 1, metal layers one through eight (i.e., layers 32, 38, 42, 50, 56, 62, 68, and 74)”, ¶ 0022. On this third metal layer 42, there is shown an etch stop layer 48, “shown in FIG. 1 are etch stop layers 46, 48 and 54, which are used to protect the dielectric layers 40, 44 and 52, respectively, during etching of trenches in the subsequently formed dielectric layers 44, 52 and 58, respectively”, ¶ 0019. The etch stop layer is formed on the entirety of the below layers, which would then satisfy, “further comprising an etching stop layer (48, ¶ 0019) disposed on an upper surface of at least one of the interlayer insulating layer (44, ¶ 0019), the upper wiring barrier layer (top surface of 42, ¶ 0019), and the upper wiring capping layer (the cap would be combined into the feature of 42, as has already been disclosed in the rejection of claim 1).”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “further comprising an etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer and the upper wiring capping layer”, as disclosed by Huang in the system of Chin, for the purpose of protecting the lower dielectric layers during etching of the trenches used to form the wiring structures. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Griggio et al. (US 2019/0304918) in view of Huang et al. (US 2004/0251549) in view of Tien et al. (US 2022/0392802).
Regarding claim 3, the prior art of Chin et al. disclose the semiconductor device of claim 2, however, as Chin does not disclose,
“further comprising a second etching stop layer in contact with the first etching stop layer on an upper surface of the first etching stop layer, wherein a second material in the second etching stop layer is different from a first material in the first etching stop layer.”
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Tien discloses in Fig. 1, the use of a “dual etch-stop layer”, for the use of “that is configured to reduce misalignment damage and improve a reliability and performance of the integrated chip.”, ¶ 0019. In Fig. 1, “The first etch-stop layer 116 comprises a first dielectric material and the second etch-stop layer 118 comprises a second dielectric material different from the first dielectric material.”, ¶ 0024. This dual etch stop could be used in the construct of Chin, where for subsequent metallization levels formed above UWL/302 of Chin in Fig. 3, the dual etch stop configuration could be utilized.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “further comprising a second etching stop layer in contact with the first etching stop layer on an upper surface of the first etching stop layer, wherein a second material in the second etching stop layer is different from a first material in the first etching stop layer.”, as disclosed by Tien in the system of Chin, for the purpose of reducing misalignment damage and improving a reliability and performance of the integrated chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Griggio et al. (US 2019/0304918) in view of Huang et al. (US 2004/0251549) in view of Tien et al. (US 2022/0392802) in view of Kang et al. (US 2022/0392841).
Regarding claim 4, the prior art of Chin et al. disclose the semiconductor device of claim 3, however, as Chin does not disclose, “further comprising a third etching stop layer in contact with the second etching stop layer on an upper surface of the second etching stop layer, wherein a third material in the third etching stop layer is different from the second material in the second etching stop layer.”
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Kang discloses in Fig. 11, the use of a “third etching stop film 313”, ¶ 0031. In Fig. 11, This triple etch stop could be used in the construct of Chin, where for subsequent metallization levels formed above UWL/302 of Chin in Fig. 3, the triple etch stop configuration could be utilized. As for the materials used in the third etch stop 313, “first etching stop film 311 and the third etching stop film 313 may be formed of or may include a material having an etching selectivity with respect to the second etching stop film 312. For example, the first etching stop film 311 and the third etching stop film 313 may be formed of or may include a metal element, and the second etching stop film 312 may not include a metal element. For example, the first etching stop film 311 and the third etching stop film 313 may be formed of or may include aluminum oxide (Al.sub.2O.sub.3). The second etching stop film 312 may be formed of or may include oxycarbide such as a silicon oxycarbide.”, ¶ 0031. This satisfies the claimed material difference between the third and second etch stop layers.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “further comprising a third etching stop layer in contact with the second etching stop layer on an upper surface of the second etching stop layer, wherein a third material in the third etching stop layer is different from the second material in the second etching stop layer.”, as disclosed by Kang in the system of Chin, for the purpose of reducing misalignment damage and improving a reliability and performance of the integrated chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 7, 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Griggio et al. (US 2019/0304918) in view of Kim et al. (US 2025/0118670).
Regarding claim 7, the prior art of Chin et al. disclose the semiconductor device of claim 6, however, as Chin does not disclose, “wherein the upper wiring barrier layer is disposed between an upper surface of the via filling layer and a lower surface of the upper wiring filling layer.”
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Kim discloses in Fig. 13, wherein the upper wiring barrier layer (“upper wiring barrier layer 151”, ¶ 0047) is disposed between an upper surface of the via filling layer (“filling layer 122”, ¶ 0039) and a lower surface of the upper wiring filling layer (“conductive layer 152_1”, ¶ 0049).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “wherein the upper wiring barrier layer is disposed between an upper surface of the via filling layer and a lower surface of the upper wiring filling layer.”, as disclosed by Kim in the system of Chin, for the purpose of fortifying the metal construction so as to further bolster the unwanted migration of the fill atoms with further barrier layer usage. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 8, the prior art of Chin et al. disclose the semiconductor device of claim 6, and Kim discloses in Fig. 13, wherein an upper surface of the via filling layer (“filling layer 122”, ¶ 0039) is in contact with a lower surface of the upper wiring filling layer (122 is in indirect contact with, “conductive layer 152_1”, ¶ 0049).
Regarding claim 14, the prior art of Chin et al. disclose the semiconductor device of claim 11, however, as Chin does not disclose, “wherein the upper wiring barrier layer is disposed between an upper surface of the via filling layer and a lower surface of the upper wiring filling layer.”
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Kim discloses in Fig. 13, wherein the upper wiring barrier layer (“upper wiring barrier layer 151”, ¶ 0047) is disposed between an upper surface of the via filling layer (“filling layer 122”, ¶ 0039) and a lower surface of the upper wiring filling layer (“conductive layer 152_1”, ¶ 0049).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “wherein the upper wiring barrier layer is disposed between an upper surface of the via filling layer and a lower surface of the upper wiring filling layer.”, as disclosed by Kim in the system of Chin, for the purpose of fortifying the metal construction so as to further bolster the unwanted migration of the fill atoms with further barrier layer usage. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 9, 15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Cheng et al. (US 2024/0038528) in view of Griggio et al. (US 2019/0304918).
Regarding claim 9, the prior art of Chin et al. disclose the semiconductor device of claim 1, however Chin does not disclose, “wherein a first vertical level of an upper surface of the upper wiring capping layer is higher than a second vertical level of an upper surface of the interlayer insulating layer.”
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Cheng discloses in Fig. 13, wherein a first vertical level of the upper surface of the upper wiring capping layer (top surface of 90) is higher than a second vertical level of the upper surface of the interlayer insulating layer (top surface of 90 is higher than top surface of 20).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the features of,
“wherein a first vertical level of an upper surface of the upper wiring capping layer is higher than a second vertical level of an upper surface of the interlayer insulating layer.”, as disclosed by Cheng in the system of Chin, for the purpose of maintaining the integrity of the wiring fill layer, by not reducing a surface level below the interlayer insulating layer, and also to simplify the method of making by not requiring a polish step to flatten the cap on the fill layer, which would prevent dishing in the interlayer insulating layer, which already had a polish to flatten the fill layer to be planar with the top of the interlayer insulating layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 15, the prior art of Chin et al. disclose the semiconductor device of claim 11, however Chin does not disclose, “wherein a first vertical level of an upper surface of the upper wiring capping layer is higher than a second vertical level of an upper surface of the interlayer insulating layer.”
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Cheng discloses in Fig. 13, wherein a first vertical level of the upper surface of the upper wiring capping layer (top surface of 90) is higher than a second vertical level of the upper surface of the interlayer insulating layer (top surface of 90 is higher than top surface of 20).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the features of,
“wherein a first vertical level of an upper surface of the upper wiring capping layer is higher than a second vertical level of an upper surface of the interlayer insulating layer.”, as disclosed by Cheng in the system of Chin, for the purpose of maintaining the integrity of the wiring fill layer, by not reducing a surface level below the interlayer insulating layer, and also to simplify the method of making by not requiring a polish step to flatten the cap on the fill layer, which would prevent dishing in the interlayer insulating layer, which already had a polish to flatten the fill layer to be planar with the top of the interlayer insulating layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 17, the prior art of Chin discloses in Figs. 2-4G, a semiconductor device (see title, “Semiconductor Devices …”) comprising:
a substrate (“substrate 202”, ¶ 0066, shown in Fig. 2);
an interlayer insulating layer (Interpreted to be insulator portions 220, 222, 224, 226, of, “ESL 208, 212, 216, 220, and/or 224, and/or another dielectric layer 206, 210, 214, 222, and/or 226”, ¶ 0074, hereinafter referred to as ‘IIL’) disposed on the substrate (on 202);
an upper wiring trench (Interpreted to be “opening 402”, ¶ 0088, as can be seen in Fig. 4A) disposed in the interlayer insulating layer (402 in IIL);
an upper wiring layer (portions of 316 and 320 specifically within 402) comprising an upper wiring barrier layer (portion of “barrier layer 316”, ¶ 0089, in 402, Fig. 4C) disposed along a sidewall and a bottom surface of the upper wiring trench (along sidewalls and bottom surface of 402),
an upper wiring filling layer (portion of “conductive structure 320”, ¶ 0083, in 402, Fig. 4F) disposed on the upper wiring barrier layer (320 on 316 in 402) so as to fill at least a portion of an inside of the upper wiring trench (320 fills remaining space in 402 after formation of 316),
an upper wiring capping layer (“a cobalt (Co) capping layer 322”, ¶ 0083, Fig. 4G) disposed on an upper surface of the upper wiring filling layer (322 on upper surface of 320).
First, Chin does not disclose,
“a first etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer and the upper wiring capping layer,
wherein a first vertical level of the upper surface of the upper wiring capping layer is higher than a second vertical level of the upper surface of the interlayer insulating layer”.
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Cheng discloses in Fig. 13, a first etching stop layer (“etch stop layer 60”, ¶ 0039) disposed on an upper surface of at least one of the interlayer insulating layer (on surface of “dielectric layer 20”, ¶ 0038), the upper wiring barrier layer (Chin already disclosed the barrier layer, but the barrier layer would be in the position of Cheng’s “liners 40’”, ¶ 0046) and the upper wiring capping layer (“cap layers 90”, ¶ 0049),
wherein a first vertical level of the upper surface of the upper wiring capping layer (top surface of 90) is higher than a second vertical level of the upper surface of the interlayer insulating layer (top surface of 90 is higher than top surface of 20).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the features of,
“a first etching stop layer disposed on an upper surface of at least one of the interlayer insulating layer, the upper wiring barrier layer and the upper wiring capping layer,
wherein a first vertical level of the upper surface of the upper wiring capping layer is higher than a second vertical level of the upper surface of the interlayer insulating layer”, as disclosed by Cheng in the system of Chin, for the purpose of maintaining the integrity of the wiring fill layer, by not reducing a surface level below the interlayer insulating layer, and also to simplify the method of making by not requiring a polish step to flatten the cap on the fill layer, which would prevent dishing in the interlayer insulating layer, which already had a polish to flatten the fill layer to be planar with the top of the interlayer insulating layer. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Chin does not disclose, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.”
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Griggio discloses in Fig. 3, wherein the “cap 360”, ¶ 0026 is a cobalt cap which is “hexagonal close packed”, see ¶ 0015, “For example, the liner and cap metals can have the same crystal structure, such as molybdenum, tantalum, and tungsten (for body centered cubic metals), or rhodium, palladium, platinum, and gold (for face centered cubic metals), or scandium, titanium, cobalt, technetium, ruthenium, cadmium, rhenium, and osmium (for hexagonal close-packed metals).” Therefore, Griggio’s disclosure satisfies, “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.” The percentage being fully of the variety disclosed, as no evidence is present to the contrary.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “wherein a volume percentage of a crystal structure having a hexagonal close-packed structure contained in the upper wiring capping layer is in a range of about 80% to about 100%.”, as disclosed by Griggio in the system of Chin, for the purpose of reducing the electromigration effects of copper in the electrical connection system. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 18, the prior art of Chin et al. disclose the semiconductor device of claim 17, and Chen discloses in Fig. 13, wherein the first etching stop layer (“etch stop layer 60”, ¶ 0039) is in contact with a sidewall of the upper wiring capping layer (60 is in contact with the sidewall of “cap layers 90”, ¶ 0049).
Regarding claim 19, the prior art of Chin et al. disclose the semiconductor device of claim 17, and Chen discloses in Fig. 13, further comprising an upper interlayer insulating layer (“dielectric layer 21”, ¶ 0040) in contact with an upper surface of the first etching stop layer on the upper surface of the first etching stop layer (21 on 60).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chin et al. (US 2023/0299002) in view of Cheng et al. (US 2024/0038528) in view of Griggio et al. (US 2019/0304918) in view of Tien et al. (US 2022/0392802).
Regarding claim 20, the prior art of Chin et al. disclose the semiconductor device of claim 17, however, as Chin does not disclose,
“further comprising a second etching stop layer in contact with the first etching stop layer on an upper surface of the first etching stop layer, wherein a second material in the second etching stop layer is different from a first material in the first etching stop layer.”
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Tien discloses in Fig. 1, the use of a “dual etch-stop layer”, for the use of “that is configured to reduce misalignment damage and improve a reliability and performance of the integrated chip.”, ¶ 0019. In Fig. 1, “The first etch-stop layer 116 comprises a first dielectric material and the second etch-stop layer 118 comprises a second dielectric material different from the first dielectric material.”, ¶ 0024. This dual etch stop could be used in the construct of Chin, where for subsequent metallization levels formed above UWL/302 of Chin in Fig. 3, the dual etch stop configuration could be utilized.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the “further comprising a second etching stop layer in contact with the first etching stop layer on an upper surface of the first etching stop layer, wherein a second material in the second etching stop layer is different from a first material in the first etching stop layer.”, as disclosed by Tien in the system of Chin, for the purpose of reducing misalignment damage and improving a reliability and performance of the integrated chip. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Double Patenting
A non-statutory double patenting rejection was considered against the Kim et al. (US 2025/0118670) reference, however, as no claims are directed to caps and in view of the elected Species I of the instant application, this Kim reference has no teachings with regard to the cap being positioned over both the planar interlevel dielectric and upper wiring fill conductor, so Kim appears to be unavailable for rejection under double patenting.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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