DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant's arguments filed 12/12/2025 have been fully considered but they are not persuasive.
In response to applicant’s arguments with regard to the independent claim 1 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… transmit the command output from the plurality of back-end chips to the second devices …” because Akavaram does not teach/suggest the above claimed feature ; applicant's arguments have fully been considered, but are not found to be persuasive.
The examiner respectfully disagrees, and to further clarify, the examiner is not relying on Akavaram, but on the combination of Burnham and Burger to teach/suggest the above claimed features. More specifically, by combining Burger’s chip (e.g. associated with back end processor being implemented on FPGA/ASIC device: [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]) with Burnham’s transmitting the command output from the plurality of back-end to the second devices (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51) (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67), the resulting combination of the references would further teach/suggest the above claimed features.
As applicant appears to be applying the above remarks for independent 1 towards independent claim 12, the examiner will also apply the above response for independent 1 towards independent claim 12.
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 and 17 of copending Application No. 17/898,975 in view of Akavaram et al. (US Patent 12,174,757). (Please note that as both the instant and copending applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and copending applications for the instant double patenting rejection)
As per claim 1, Copending Application No. 17/898,975 teaches/suggests a device for implementing a storage architecture, comprising: a front-end chip configured to perform first interfacing with a first device through a first interface standard; a plurality of back-end chips configured to perform a second interfacing with second devices, communicate with the front-end chip through a second interface standard, and output to the second devices; and operating from the front-end chip and the plurality of back-end chips, and configured to perform a communication between the second devices and the plurality of back-end chips, communicate with the plurality of back-end chips through the second interface standard and transmit output from the plurality of back-end chips to the second devices (Claim 1 and claim 17).
Copending Application No. 17/898,975 does not teach a device comprising
a command to control; and
an input/output chip disposed to be separated, and having the command.
Burnham teaches/suggests a device comprising: a command to control (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module disposed to be separated (e.g. associated with I/O adapter: Fig. 2; col. 8, ll. 34-40), and having the command (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Akavaram teaches/suggests a device comprising: a chip (e.g. associated with I/O die (108) in Fig. 1) operating accordingly (Fig. 1; and col. 5, l. 50 to col. 6, l. 12)
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burnham’s front-end and back-end operations and Akavaram’s I/O circuit into Copending Application No. 17/898,975’s device to obtain the invention as specified in claim 1.
This is a provisional nonstatutory double patenting rejection.
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), Akavaram et al. (US Patent 12,174,757).
As per claim 1, Burnham teaches/suggests a device for implementing a storage architecture, comprising: a front-end (e.g. associated with front end director (180) of Fig. 2) configured to perform first interfacing (e.g. associated with port interface (123) between front end director (180) and host computer (120) with corresponding processor (121) in Fig. 2) with a first device through a first interface standard (e.g. associated with host computer (120) with corresponding processor (121) communicating with front end director (180) via corresponding communication protocol/standard in Fig. 2); a plurality of back-end (e.g. associated with plurality of back end directors (200) in Fig. 2) configured to perform a second interfacing (e.g. associated with port interface (123) between back end directors (200) and disk drives (141) in Fig. 2) with second devices (e.g. associated with disk drives (141) in Fig. 2), communicate with the front end through a second interface standard, and output a command to control the second devices (e.g. associated with properly coordinating bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module (e.g. associated with I/O adapter: col. 8, ll. 34-40) disposed to be separate from the front-end (e.g. associated with front end director (180) of Fig. 2: col. 8, ll. 34-40 ) and the plurality of back-end (e.g. associated with plurality of back end directors (200) in Fig. 2: col. 8, ll. 34-40), and configured to perform a communication between the second devices and the plurality of back-end chips (e.g. associated with communication between the disk drives (141) and the back end directors (200) in Fig. 1), communicate with the plurality of back-end through the second interface standard and transmit the command output from the plurality of back-end to the second devices (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51) (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Burnham does not teach the device comprising:
a first chip;
a second chip, with the first chip operating accordingly; and
a third operating with the first chip and the second chip, and operating with the second chip, operating with the second chip accordingly and operating with the second chip accordingly.
Burger teaches/suggests a device comprising: a first chip (e.g. associated with front end processor being implemented on FPGA/ASIC device: [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]); a second chip (e.g. associated with back end processor being implemented on FPGA/ASIC device: [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]) with the first chip operating accordingly (e.g. associated with front end processor operating accordingly: [0019]-[0020]; [0035]-[0038]; [0045]-[0047]; and [0128]-[0129]), operating with the first chip and the second chip, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly (e.g. associated with operating with front end processor and back end processor) (Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; and [0128]-[0129]).
Akavaram teaches/suggests a device comprising: an third chip (e.g. associated with I/O die (108) in Fig. 1) operating accordingly (Fig. 1; and col. 5, l. 50 to col. 6, l. 12).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s separated circuits and Akavaram’s I/O circuit into Burnham’s device for the benefit of reducing compression time while maintaining compression quality (Burger, [0019]) and achieving power conservation while reducing latency when transition from lower power state (Akavaram, col. 5, ll. 27-36) to obtain the invention as specified in claim 1.
As per claim 2, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the front-end chip, the plurality of back-end chips and the input/output chip are configured in a chiplet structure in which the front-end chip, the plurality of back-end chips and the input/output chip are physically separated to function independently of each other (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 3, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the front-end chip, the plurality of back-end chips and the input/output chip are configured to be independently replaceable in response to any changes in a specification of at least one of the first device and the second devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13), wherein if would have been obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as the chips are implemented as independent/separate ASICs (Goergen et al. (US Pub.: 2021/0382967): disclose components such as ASIC may be replaceable [0003])..
As per claim 6, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is a universal chiplet interconnect express (UCIe) standard (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 8, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the front-end chip, the plurality of back-end chips and the input/output chip are disposed on a same package substrate (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 9, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the first device is a host device, and the second devices are memory devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 10, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein each of the second devices includes at least one of a volatile memory device, a non-volatile memory device, or an accelerator memory device (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 11, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the front-end chip is configured to communicate with a first memory device, and the plurality of back-end chips are configured to communicate with a second memory device, and a type of the first memory device is different from a type of the second memory device (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
As per claim 16, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the command is transmitted from the front-end chip to at least one of the plurality of back-end chips, and data responding to the command is transmitted from the second devices to the front-end chip through the at least one of the plurality of back-end chips (e.g. associated with properly coordinating with bank of disk drives to carry out read operation(s) via corresponding control/command signaling as requested by host computer/server) (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), and Akavaram et al. (US Patent 12,174,757) as applied to claim 1 above, and further in view of BUSAYARAT et al. (US Pub.: 2018/0253493).
As per claim 7, Burnham, Burger, and Akavaram teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the input/output chip communicates a signal transmission between the plurality of back-end chips and the second devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13), but Burnham, Burger, and Akavaram do not teach including a multiplexer or de-multiplexer configured to control signaling.
BUSAYARAT teach/suggest a device comprising including a multiplexer (e.g. associated with Fig. 3, ref. 352) or de-multiplexer (e.g. associated with Fig. 4, ref. 452) configured to control signaling (Fig. 3-4; [0019]-[0023]; and [0049]-[0050]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include BUSAYARAT’s multiplexing/de-multiplexing into Burnham, Burger, and Akavaram’s device architecture for the benefit of facilitating efficient data response while conserving considerable computing and network resources (BUSAYARAT, [0079]) to obtain the invention as specified in claim 7.
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), Bhagavat et al. (US Pub.: 2020/0185367), and Akavaram et al. (US Patent 12,174,757).
As per claim 12, Burnham teaches/suggests a device for implementing a storage architecture, comprising: at least one memory device (e.g. associated with global cache memory (220)/local cache memory (RAM): col. 4, ll. 41-61); and a controller, and configured to control the at least one memory device, wherein the controller comprises, a front-end (e.g. associated with front end director (180) of Fig. 2) configured to perform a communication with a host device through a first interface standard (e.g. associated with host computer (120) with corresponding processor (121) communicating with front end director (180) via corresponding communication protocol/standard in Fig. 2), at least one back-end (e.g. associated with back end director (200) in Fig. 2) configured to perform a communication with at least one memory device (e.g. associated with global cache memory (220)/local cache memory (RAM) communicating with back end director (200) in Fig. 2: col. 4, ll. 41-61; col. 6, ll. 50-65), communicate with the front end through a second interface standard, and output a command to control the at least one memory device (e.g. associated with properly coordinating bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module (e.g. associated with I/O adapter: col. 8, ll. 34-40) operating with the front-end (e.g. associated with front end director (180) of Fig. 2) and the at least one back-end (e.g. associated with plurality of back end directors (200) in Fig. 2), and configured to perform a communication between the at least one memory device and the at least one back-end (e.g. associated with communication between the disk drives (141) and the back end directors (200) in Fig. 1), communicate with the at least one back-end through the second interface standard and transmit the command output from the at least one of back-end to the at least one memory device (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51) (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Burnham does not teach the device comprising:
being disposed on a substrate; and
package located on the substrate, wherein the package comprises, a first chip, a second chip, with the first chip operating accordingly; and
an third chip operating with the first chip and the second chip, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly.
Burger teaches/suggests a device comprising: comprises, a first chip (e.g. associated with front end processor being implemented on FPGA/ASIC device: [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]), a second chip (e.g. associated with back end processor being implemented on FPGA/ASIC device: [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]), with the first chip operating accordingly (e.g. associated with front end processor operating accordingly: [0019]-[0020]; [0035]-[0038]; [0045]-[0047]; and [0128]-[0129]); and operating with the first chip and the second chip, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly (e.g. associated with operating with front end processor and back end processor) (Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; and [0128]-[0129]).
Bhagavat teaches/suggests a device comprising: being disposed on a substrate (e.g. associated with package substrate: [0025]); and package located on the substrate, wherein the package comprises chip (e.g. associated with integrated circuit die in package on package substrate: [0019]-[0020]; [0022]; [0025]) (Fig. 2; Fig. 8, Fig. 12D; [0021]-[0025]; and [0033]-[0037]).
Akavaram teaches/suggests a device comprising: an third chip (e.g. associated with I/O die (108) in Fig. 1) (Fig. 1; col. 5, l. 50 to col. 6, l. 12).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s separated circuits, Bhagavat’s packaging, and Akavaram’s I/O circuit into Burnham’s device for the benefit of reducing compression time while maintaining compression quality (Burger, [0019]), reducing space on substrate for discreet components in a packaged integrated circuit module (Bhagavat, [0037]), and achieving power conservation while reducing latency when transition from lower power state (Akavaram, col. 5, ll. 27-36)to obtain the invention as specified in claim 12.
As per claim 15, Burnham, Burger, Bhagavat, and Akavaram teach/suggest all the claimed features of claim 13 above, where Burnham, Burger, Bhagavat, and Akavaram further teach/suggest the device for the storage architecture comprising wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is a universal chiplet interconnect express (UCIe) standard (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Bhagavat, Fig. 2; Fig. 8, Fig. 12D; [0021]-[0025]; [0033]-[0037]; and Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13).
II. PERTINENT RELATED PRIOR ART
Gay et al. (US Pub.: 2018/0063280): discloses a client communicated with data source(s) via front-end data service and back-end data service.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 February 13, 2026