DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/19/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-3, 6-7, 9-12, and 15-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 17 of U.S. Patent No. 12,613,814 in view of Burnham (US Patent 6,597,232), Akavaram et al. (US Patent 12,174,757), and Nalamalpu et al. (US Pub.: 2022/0337251). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
As per claim 1, U.S. Patent No. 12,613,814 teaches/suggests a device for implementing a storage architecture, comprising: a front-end chip configured to perform first interfacing with a first device through a first interface standard; a plurality of back-end chips disposed to be physically separated from the front end chip, and configured to perform a second interfacing with second devices, communicate with the front-end chip through a second interface standard, and output to the second devices; and operating from the front-end chip and the plurality of back-end chips, and configured to perform a communication between the second devices and the plurality of back-end chips, communicate with the plurality of back-end chips through the second interface standard and transmit output from the plurality of back-end chips to the second devices (Claim 1 and claim 17).
U.S. Patent No. 12,613,814 does not teach a device comprising
being disposed on a package substrate, and being disposed outside of the package substrate;
being on the package substrate, and being disposed outside of the package indirectly, a command to control; and
an input/output chip disposed to be physically separated on the package substrate, operating directly, communicating with the second device through an interface standard different from the first interface standard and the second interface standard directly, and having the command.
Burnham teaches/suggests a device comprising: being disposed outside (e.g. associated with host computer (120) with corresponding processor (121) being disposed outside in Fig. 2);being disposed outside (e.g. associated with disk drives (141) being disposed outside in Fig. 2), and a command to control (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module disposed to be separated (e.g. associated with I/O adapter: Fig. 2; col. 8, ll. 34-40), operating directly (e.g. associated with I/O adapter directly communicating with the back-end director in accordance to back-end director interface standard), communicating with the second device through an interface standard different from the first interface standard and the second interface standard directly (e.g. associated with I/O adapter directly communicating with disk drive in accordance to disk drive interface standard, which is different from front-end interface standard and back-end interface standard), and having the command (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Akavaram teaches/suggests a device comprising: operating indirectly (e.g. associated with communicating indirectly via I/O die (108) of Fig. 1); and a chip being physically separated (e.g. associated with physically separated I/O die (108) in Fig. 1) operating accordingly (Fig. 1; and col. 5, l. 50 to col. 6, l. 12).
Nalamalpu teaches/suggests a device comprising: being disposed on a package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the package substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0036]); being disposed on a package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the package substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0036]); and being on the package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]) (Fig. 3-5; and [0019]-[0041]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burnham’s front-end and back-end operations, Akavaram’s I/O circuit, and Nalamalpu’s circuit architecture into Copending Application No. 17/898,975’s device to obtain the invention as specified in claim 1.
This is a provisional nonstatutory double patenting rejection.
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 9-11 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), Akavaram et al. (US Patent 12,174,757), and Nalamalpu et al. (US Pub.: 2022/0337251).
As per claim 1, Burnham teaches/suggests a device for implementing a storage architecture, comprising: a front-end (e.g. associated with front end director (180) of Fig. 2) configured to perform a first interfacing (e.g. associated with port interface (123) between front end director (180) and host computer (120) with corresponding processor (121) in Fig. 2) with a first device disposed outside through a first interface standard (e.g. associated with outside host computer (120) with corresponding processor (121) communicating with front end director (180) via front-end interface standard having corresponding communication protocol/standard in Fig. 2); a plurality of back-end (e.g. associated with plurality of back end directors (200) in Fig. 2) separated from the front-end (e.g. associated with front end director (180) being separated from plurality of back end directors (200) in Fig. 2) configured to perform a second interfacing (e.g. associated with port interface (123) between back end directors (200) and disk drives (141) in Fig. 2) with second devices disposed outside (e.g. associated with outside disk drives (141) in Fig. 2), communicate with the front end through a second interface standard, and output a command to control the second devices (e.g. associated with properly coordinating bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module (e.g. associated with I/O adapter between back-end director and disk drive: col. 8, ll. 34-40) disposed to be separate from the front-end (e.g. associated with front end director (180) of Fig. 2: col. 8, ll. 34-40 ) and the plurality of back-end (e.g. associated with plurality of back end directors (200) in Fig. 2: col. 8, ll. 34-40), and configured to perform a communication between the second devices and the plurality of back-end (e.g. associated with communication between the disk drives (141) and the back end directors (200) in Fig. 1), communicate with the plurality of back-end through the second interface standard directly (e.g. associated with I/O adapter directly communicating with the back-end director in accordance to back-end director interface standard), communicate with the second device through an interface standard different from the first interface standard and the sconed interface standard directly (e.g. associated with I/O adapter directly communicating with disk drive in accordance to disk drive interface standard, which is different from front-end interface standard and back-end interface standard), and transmit the command output from the plurality of back-end to the second devices (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51) (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Burnham does not teach the device comprising:
a first chip disposed on a package substrate, and operating accordingly with outside of the package substrate;
a second chip disposed to be physically separate from the first chip on the package substrate, and operating accordingly with outside of the package substrate indirectly, operating with the first chip; and
a third chip physically separated from the first chip and the second chip on the package substrate, and operating with the second chip, operating with the second chip accordingly and operating with the second chip accordingly.
Burger teaches/suggests a device comprising: a first chip (e.g. associated with front end processor being implemented on FPGA/ASIC/custom integrated circuit device(s): [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]); a second chip disposed to be physically separate from the first chip (e.g. associated with back end processor being implemented on another FPGA/ASIC/custom integrated circuit device(s): [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]), and operating with the first chip (e.g. associated with front end processor operating accordingly: [0019]-[0020]; [0035]-[0038]; [0045]-[0047]; and [0128]-[0129]); and operating with the first chip and the second chip, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly (e.g. associated with operating with front end processor and back end processor) (Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; and [0128]-[0129]).
Akavaram teaches/suggests a device comprising: operating indirectly (e.g. associated with communicating indirectly via I/O die (108) of Fig. 1); and an third chip being physically separated (e.g. associated with physically separated I/O die (108) in Fig. 1) operating accordingly (Fig. 1; and col. 5, l. 50 to col. 6, l. 12).
Nalamalpu teaches/suggests a device comprising: being disposed on a package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the package substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0036]); being disposed on the package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the package substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0031]; [0036]); and being on the package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]) (Fig. 3-5; and [0019]-[0041]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s separated circuits, Akavaram’s I/O circuit, and Nalamalpu’s circuit architecture into Burnham’s device for the benefit of reducing compression time while maintaining compression quality (Burger, [0019]), achieving power conservation while reducing latency when transition from lower power state (Akavaram, col. 5, ll. 27-36), and shortening the time to develop the integrated circuit system (Nalamalpu, [0022]) to obtain the invention as specified in claim 1.
As per claim 2, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the front-end chip, the plurality of back-end chips and the input/output chip are configured in a chiplet structure in which the front-end chip, the plurality of back-end chips and the input/output chip are physically separated to function independently of each other (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
As per claim 3, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the front-end chip, the plurality of back-end chips and the input/output chip are configured to be independently replaceable in response to any changes in a specification of at least one of the first device and the second devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]), wherein if would have been obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as the chips are implemented as independent/separate ASICs (Goergen et al. (US Pub.: 2021/0382967): disclose components such as ASIC may be replaceable [0003])..
As per claim 6, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is a universal chiplet interconnect express (UCIe) standard (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
As per claim 9, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the first device is a host device, and the second devices are memory devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
As per claim 10, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein each of the second devices includes at least one of a volatile memory device, a non-volatile memory device, or an accelerator memory device (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
As per claim 11, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the front-end chip is configured to communicate with a first memory device, and the plurality of back-end chips are configured to communicate with a second memory device, and a type of the first memory device is different from a type of the second memory device (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
As per claim 16, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the command is transmitted from the front-end chip to at least one of the plurality of back-end chips, and data responding to the command is transmitted from the second devices to the front-end chip through the at least one of the plurality of back-end chips (e.g. associated with properly coordinating with bank of disk drives to carry out read operation(s) via corresponding control/command signaling as requested by host computer/server) (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), Akavaram et al. (US Patent 12,174,757), and Nalamalpu et al. (US Pub.: 2022/0337251) as applied to claim 1 above, and further in view of BUSAYARAT et al. (US Pub.: 2018/0253493).
As per claim 7, Burnham, Burger, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 1 above, where Burnham, Burger, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the input/output chip communicates a signal transmission between the plurality of back-end chips and the second devices (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]), but Burnham, Burger, Akavaram, and Nalamalpu do not teach including a multiplexer or de-multiplexer configured to control signaling.
BUSAYARAT teach/suggest a device comprising including a multiplexer (e.g. associated with Fig. 3, ref. 352) or de-multiplexer (e.g. associated with Fig. 4, ref. 452) configured to control signaling (Fig. 3-4; [0019]-[0023]; and [0049]-[0050]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include BUSAYARAT’s multiplexing/de-multiplexing into Burnham, Burger, Akavaram, and Nalamalpu’s device architecture for the benefit of facilitating efficient data response while conserving considerable computing and network resources (BUSAYARAT, [0079]) to obtain the invention as specified in claim 7.
Claims 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Burnham (US Patent 6,597,232) in view of Burger et al. (US Pub.: 2017/0147624), Bhagavat et al. (US Pub.: 2020/0185367), Akavaram et al. (US Patent 12,174,757), and Nalamalpu et al. (US Pub.: 2022/0337251).
As per claim 12, Burnham teaches/suggests a device for implementing a storage architecture, comprising: at least one memory device (e.g. associated with global cache memory (220)/local cache memory (RAM): col. 4, ll. 41-61); and a controller, and configured to control the at least one memory device, wherein the controller comprises, a front-end (e.g. associated with front end director (180) of Fig. 2) configured to perform a communication with a host device located outside through a first interface standard (e.g. associated with outside host computer (120) with corresponding processor (121) communicating with front end director (180) via front-end interface standard having corresponding communication protocol/standard in Fig. 2), at least one back-end (e.g. associated with back end director (200) in Fig. 2) separated from the front end (e.g. associated with front end director (180) being separated from plurality of back end directors (200) in Fig. 2), and configured to perform a communication with at least one memory device disposed outside (e.g. associated with communicating with outside disk drives (141) in Fig. 2), communicate with the front end through a second interface standard, and output a command to control the at least one memory device (e.g. associated with properly coordinating bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51); and an input/output module (e.g. associated with I/O adapter between back-end director and disk drive: col. 8, ll. 34-40) disposed to be separate from the front-end (e.g. associated with front end director (180) of Fig. 2: col. 8, ll. 34-40 ) and the at least one back-end (e.g. associated with plurality of back end directors (200) in Fig. 2: col. 8, ll. 34-40), and configured to perform a communication between the at least one memory device and the at least one back-end (e.g. associated with communication between the disk drives (141) and the back end directors (200) in Fig. 1), communicate with the at least one back-end through the second interface standard directly (e.g. associated with I/O adapter directly communicating with the back-end director in accordance to back-end director interface standard), communicate with the second device through an interface standard different from the first interface standard and the sconed interface standard directly (e.g. associated with I/O adapter directly communicating with disk drive in accordance to disk drive interface standard, which is different from front-end interface standard and back-end interface standard), and transmit the command output from the at least one of back-end to the at least one memory device (e.g. associated with properly coordinating with bank of disk drives to carry out read/write operation(s) via corresponding control/command signaling as requested by host computer/server: col. 1, l. 60 to col. 2, l. 56; col. 5, l. 46 to col. 7, l. 51) (Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; and col. 9, ll. 56-67).
Burnham does not teach the device comprising:
being disposed on a substrate; and
package located on the substrate, wherein the package comprises,
a first chip disposed on a package substrate, and operating accordingly with outside of the package substrate,
a second chip disposed to be physically separate from the first chip on the package substrate, and operating accordingly with outside of the package substrate indirectly, operating with the first chip; and
an third chip physically separated from the first chip and the second chip on the package substrate, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly.
Burger teaches/suggests a device comprising: comprises, a first chip (e.g. associated with front end processor being implemented on FPGA/ASIC/custom integrated circuit device(s): [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]), a second chip disposed to be physically separate from the first chip (e.g. associated with back end processor being implemented on another FPGA/ASIC/custom integrated circuit device(s): [0019]-[0020]; [0035]-[0038]; [0046]; and [0128]-[0129]), operating with the first chip (e.g. associated with front end processor operating accordingly: [0019]-[0020]; [0035]-[0038]; [0045]-[0047]; and [0128]-[0129]); and operating with the first chip and the second chip, and operate with the second chip, operating with the second chip accordingly and operating with the second chip accordingly (e.g. associated with operating with front end processor and back end processor) (Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; and [0128]-[0129]).
Bhagavat teaches/suggests a device comprising: being disposed on a substrate (e.g. associated with package substrate: [0025]); and package located on the substrate, wherein the package comprises chip (e.g. associated with integrated circuit die in package on package substrate: [0019]-[0020]; [0022]; [0025]) (Fig. 2; Fig. 8, Fig. 12D; [0021]-[0025]; and [0033]-[0037]).
Akavaram teaches/suggests a device comprising: operating indirectly (e.g. associated with communicating indirectly via I/O die (108) of Fig. 1); and an third chip being physically separated (e.g. associated with physically separated I/O die (108) in Fig. 1) operating accordingly (Fig. 1; and col. 5, l. 50 to col. 6, l. 12).
Nalamalpu teaches/suggests a device comprising: being disposed on a package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0036]); being disposed on the package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]), and operating accordingly with outside of the package substrate (e.g. associated with communicating outside of the package of the integrated circuit system: [0031]; [0036]); and being on the package substrate (e.g. associated with Fig. 4-5, ref. 234: [0036]) (Fig. 3-5; and [0019]-[0041]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Burger’s separated circuits, Bhagavat’s packaging, Akavaram’s I/O circuit, and Nalamalpu’s circuit architecture into Burnham’s device for the benefit of reducing compression time while maintaining compression quality (Burger, [0019]), reducing space on substrate for discreet components in a packaged integrated circuit module (Bhagavat, [0037]), achieving power conservation while reducing latency when transition from lower power state (Akavaram, col. 5, ll. 27-36), and shortening the time to develop the integrated circuit system (Nalamalpu, [0022]) to obtain the invention as specified in claim 12.
As per claim 15, Burnham, Burger, Bhagavat, Akavaram, and Nalamalpu teach/suggest all the claimed features of claim 13 above, where Burnham, Burger, Bhagavat, Akavaram, and Nalamalpu further teach/suggest the device for the storage architecture comprising wherein the first interface standard is a compute express link (CXL) standard or a peripheral component interconnect express (PCIe) standard, and the second interface standard is a universal chiplet interconnect express (UCIe) standard (Burnham, Fig. 2-3; Fig. 7; col. 1, l. 60 to col. 2, l. 56; col. 4, l. 41 to col. 8, l. 43; col. 9, ll. 56-67; Burger, Fig. 1; Fig. 4A-4B; [0019]-[0027]; [0032]-[0039]; [0045]-[0047]; [0128]-[0129]; Bhagavat, Fig. 2; Fig. 8, Fig. 12D; [0021]-[0025]; [0033]-[0037]; Akavaram, Fig. 1; col. 3, ll. 26-55; col. 5, l. 50 to col. 6, l. 12; col. 7, l. 63 to col. 8, l. 13; and Nalamalpu, Fig. 3-5; [0019]-[0041]).
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-3, 6-7, 9-12, and 15-16 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 June 17, 2026
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