Prosecution Insights
Last updated: April 19, 2026
Application No. 18/644,090

ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Apr 23, 2024
Examiner
SHARMA, ADITYA
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
18 granted / 20 resolved
+22.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
18 currently pending
Career history
38
Total Applications
across all art units

Statute-Specific Performance

§103
60.8%
+20.8% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 20 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a2) as being anticipated by Wu et al. (US 20230317904 A1) Regarding Claim 1 – Wu discloses an electronic device, comprising: a flexible substrate (Fig 2B; FSB); a plurality of electronic elements disposed on the flexible substrate (Fig 2B; LE(EL)), wherein three adjacent ones of the plurality of electronic elements are arranged as a group to form an electronic unit (Fig 2B shows the three-bar group in each block) such that the plurality of electronic elements form a plurality of electronic units (Fig 2B shows four repeated blocks, each containing a three element group), and four adjacent ones of the plurality of electronic units form a unit region that is quadrilateral (Fig 2B shows the 2x2 block arrangement as a quadrilateral region); a plurality of wires disposed on the flexible substrate (Fig 2B; CW on FSB), a plurality of electrical connection holes(fig 3B, BP) disposed on the flexible substrate(fig 3B, EG), wherein a density of the electrical connection holes in a peripheral portion of the unit region is greater than a density of the electrical connection holes in a central portion of the unit region(the holes are distributed along the dotted line if fig 1, thus the electrical connection holes are greater in a peripheral portion of the unit region than in the center since they are not present in the center). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230317904 A1) and in further view of Mingzhan et al. (CN 110972389 A) Regarding Claim 2 – Wu in view of Zhang teaches the electronic device according to claim 1, but fails to disclose wherein the plurality of electrical connection holes are disposed adjacent to the plurality of electronic elements. Mingzhan teaches the plurality of electrical connection holes are disposed adjacent to the plurality of electronic elements (Fig 2; 121/111; Mingzhan [Detailed description] states “The connection hole 121 is provided adjacent to the mounting area 111… at least one connection hole 121 is provided around each mounting area 111”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Wu in view of Zhang with the plurality of electrical connection holes are disposed adjacent to the plurality of electronic elements as taught by Mingzhan because Mingzhan states “it is necessary to increase the mounting density of electronic components. However, if the mounting density is increased… it is more and more difficult to install the metal cover. In order to make it suitable for high-density circuit boards”. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230317904 A1) and in further view of Guo et al. (US 20210013242 A1) Regarding Claim 4 – Wu in view of Zhang teaches the electronic device according to claim 1, but fails to disclose wherein the plurality of electronic elements are electrically connected to the plurality of wires through at least one of the plurality of electrical connection holes respectively. Guo teaches the plurality of electronic elements are electrically connected to the plurality of wires through at least one of the plurality of electrical connection holes respectively (Fig 6; 123; Guo [0072] states “a via hole 123 is formed on the second sub-substrate 12”; Figs 2-3; 14; Guo [0076] states “the pixel array layer 14 is electrically connected to the wiring through the via hole 123” and Guo [0006] states “the gate is electrically connected to the gate line through the via hole, and the source is electrically connected to the data line through the via hole”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Wu in view of Zhang with the plurality of electronic elements are electrically connected to the plurality of wires through at least one of the plurality of electrical connection holes respectively as taught by Guo because Guo [0004] states the flexible array substrate “can reduce the difficulty of wiring, decrease the IR drop, and improve the problem that the wiring is prone to breakage when bent”. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230317904 A1) and in further view of Yueh et al. (US 10561029 B1) Regarding Claim 5 – Wu in view of Zhang teaches the electronic device according to claim 1, but fails to disclose wherein the plurality of electronic units comprises a first electronic unit and a second electronic unit, the first electronic unit and the second electronic unit are adjacent to each other in a first direction and have an shifting distance in a second direction, wherein the second direction is perpendicular to the first direction, and the first electronic unit has a first length in the second direction, wherein the shifting distance is greater than or equal to 0.2 times of the first length and less than or equal to 0.5 times of the first length. Yueh teaches the plurality of electronic units comprises a first electronic unit and a second electronic unit (Fig 2; 208 and 210), the first electronic unit and the second electronic unit are adjacent to each other in a first direction (Fig 2; pitch P1defined between the first electronic units in adjacent rows “in the direction 1”; and pitch P2 defined between the second electronic units in adjacent rows “in the direction 1”) and have an shifting distance in a second direction (Fig 2; shifting distance S), wherein the second direction is perpendicular to the first direction (Fig 2; directions 1 and 2; Yueh [Detailed description] states “the direction 2 may be substantially perpendicular to the direction 1”), and the first electronic unit has a first length in the second direction (Fig 2; Yueh’s electronic units necessarily have a dimension (length) in direction 2, since direction 2 is a defined axis of the layout), wherein the shifting distance is greater than or equal to 0.2 times of the first length and less than or equal to 0.5 times of the first length (Yueh states “If the shifting distance S is less than (P1+P2)/6… shift… above will still be obvious” and “if… greater than (P1+P2)/4… affect the image displayed”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Wu in view of Zhang with the plurality of electronic units comprises a first electronic unit and a second electronic unit, the first electronic unit and the second electronic unit are adjacent to each other in a first direction and have an shifting distance in a second direction, wherein the second direction is perpendicular to the first direction, and the first electronic unit has a first length in the second direction, wherein the shifting distance is greater than or equal to 0.2 times of the first length and less than or equal to 0.5 times of the first length as taught by Yueh because Yueh states “With this shifting design… the tolerance of the shift caused by the processing error becomes high. Therefore, fewer electronic devices will have to be scrapped”. Further, in view of Yueh’s teaching (quoted above) that the shifting distance should not be too small or too large to avoid an obvious shift and to avoid affecting the displayed image, a person skilled in the art would have routinely selected the shifting distance to satisfy the claimed proportional range relative to the unit length. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230317904 A1) and Yueh et al. (US 10561029 B1) and in further view of Hirayama et al. (US 20050083400 A1) Regarding Claim 6 – Wu in view of Zhang and Yueh teaches the electronic device according to claim 1, wherein in the second direction, the plurality of electronic elements of the first electronic unit has a second length respectively (Yueh [Detailed description] states “one electronic unit may include a plurality of electronic elements, such as chips or dies”), and a spacing exists between two adjacent ones of the plurality of electronic elements of the first electronic unit (Wu; Fig 2B shows spacing/gaps between the plurality of elements). Wu in view of Zhang and Yueh fails to disclose the shifting distance is not equal to N times of a sum of the second length and the spacing, and N is a positive integer. Hirayama teaches the shifting distance is not equal to N times of a sum of the second length and the spacing, and N is a positive integer (Hirayama [0040] states “the vertical pitch of the apertures is not equal to an integer multiple of the pixel pitch”). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Wu in view of Zhang and Yueh with the shifting distance is not equal to N times of a sum of the second length and the spacing, and N is a positive integer as taught by Hirayama because Hirayama states “required design accuracy need not be so high” and that “flipping does not occur”, evidencing and advantage of selecting a non-integer-multiple pitch relationship. Claims 7-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 20230317904 A1) and in further view of Yamada (US 20150069453 A1) Regarding Claim 7 – Wu in view of Zhang teaches the electronic device according to claim 1, but fails to disclose further comprising a plurality of reinforcing structures disposed on the flexible substrate, wherein the plurality of reinforcing structures are disposed adjacent to at least one of the plurality of electronic elements respectively. Yamada teaches a plurality of reinforcing structures disposed on the flexible substrate (Fig 1B; projections 4 on flexible substrate member 1; Yamada [0008] states “The flexible substrate member includes a plurality of projections… the metal wirings have been reinforced by the projections”), wherein the plurality of reinforcing structures are disposed adjacent to at least one of the plurality of electronic elements respectively (Fig 4B; 6; Yamada [0019] states “a mounting portion 6 for connecting a light emitting element 9 is formed” and Yamada [0008] quoted above). It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Wu in view of Zhang with a plurality of reinforcing structures disposed on the flexible substrate, wherein the plurality of reinforcing structures are disposed adjacent to at least one of the plurality of electronic elements respectively as taught by Yamada because Yamada teaches the reinforcing pattern is “for imparting rigidity to the flexible substrate member” and that “breakage of the metal wirings can be prevented” by enforcing with projections (Yamada [0005, 0008]). Regarding Claim 8 - Wu in view of Zhang and Yamada teaches the electronic device according to claim 7, wherein the plurality of reinforcing structures comprises a first reinforcing structure having an extending portion (Yamada Fig 1B; 33) and a protruding portion (Yamada Fig 1B; 4 protruding from 33) protruding from the extending portion, an extension direction of the extending portion is parallel to a long-axis direction of one of the plurality of electronic elements (Wu Fig 2B; LE(EL) shown as elongate bar shaped elements defining long axis; Yamada Fig 1B; extending portion 33 extends in a direction parallel to the long axis of LE(EL)). Regarding Claim 10 - Wu in view of Zhang and Yamada teaches the electronic device according to claim 7, further comprising an extension metal line disposed on the flexible substrate (Fig 1B; 3 disposed on 1; Yamada [0019] states “portions of the metal wiring 3 are extended toward each other”), wherein the plurality of reinforcing structures comprises a second reinforcing structure in contact with the extension metal line (Yamada Fig 1B; 4 on 33; Yamada [0021] states “each of the projections 4 is formed in the third metal wiring 33”). Allowable Subject Matter Claim(s) 3, 9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 11-20 allowed. The following is an examiner’s statement of reasons for allowance: The prior art does not teach or suggest an electronic device with “a plurality of electronic elements disposed on the flexible substrate, wherein three adjacent ones of the plurality of electronic elements form a second region, and the first region is overlapped with the second region, wherein an area ratio of the first region to the second region is greater than 1 and less than or equal to 9” for claim 11; in combination with all other features claimed. Regarding claims 12-20, these claims are allowed based on their dependence on the allowable claim 11 discussed above. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADITYA SHARMA/ Examiner, Art Unit 2847 /TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Apr 23, 2024
Application Filed
Mar 02, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12588141
CIRCUIT BOARD ARRANGEMENT COMPRISING A CIRCUIT BOARD PROVIDED WITH A GRAPHENE ISLAND AND METHOD OF COMMUNICATING BETWEEN A FIRST AND A SECOND CIRCUIT
2y 5m to grant Granted Mar 24, 2026
Patent 12586611
ELECTRONIC DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12575029
WIRING BOARD
2y 5m to grant Granted Mar 10, 2026
Patent 12550698
VIA PROFILE SHRINK FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
2y 5m to grant Granted Feb 10, 2026
Patent 12545200
GROMMET FOR VEHICLE AND METHOD OF ASSEMBLING GROMMET ASSEMBLY FOR VEHICLE
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+16.7%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 20 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month