DETAILED ACTION
This Notice is responsive to communication filed on 07/22/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 17/701,678, filed on 03/23/2022.
Election/Restrictions
Applicant’s election without traverse of Species 4, reading on Fig. 9, 10, and 11-11C in the reply filed on 07/22/2026 is acknowledged.
Claim 12 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/22/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220068193), and further in view of and Kang et al. (US 20090224262).
Regarding claim 1, Wang discloses:
a micro light emitting diode panel (Fig. 1, 7), comprising:
a circuit substrate Fig. 7: 120, comprising:
a plurality of signal lines Fig. 1: SL/DL, composed of a plurality of metal conductive layers Fig. 7: 131 (para. 0052) and defining a plurality of pixel areas Fig. 1: 110;
a plurality of bonding pads Fig. 7: PD/132 (para. 0050), extending from at least part of the signal lines Fig. 1: SL/DL; and
a plurality of thin film transistors Fig. 1: T1, formed on the circuit substrate Fig. 7: 120,
wherein each of the thin film transistors Fig. 7: T1 has a first semiconductor pattern (para. 0060 teaches T1, a TFT has a larger on-resistance; para. 0045 teaches T1 may also be an FET which can be a MOSFET (para. 0043)) and a plurality of electrodes Fig. 7: S1/D1/G1 composed of the metal conductive layers Fig. 7: 131, and
the electrodes Fig. 7: S1/D1/G1 are electrically connected to at least part of the bonding pads Fig. 7: PD/132 (shown in Fig. 7); and
a plurality of transfer units Fig. 7: 112+T2, electrically bonded to a part of the bonding pads Fig. 7: PD/132 and electrically connected to the thin film transistors Fig. 7: T1, each of the transfer units Fig. 7: 112+T2 includes:
a micro light emitting diode Fig. 1: 112; and
a transistor element Fig. 1: T2, having a second semiconductor pattern (para. 0043, channel material – polysilicon; teaches small on-resistance), and electrically connected to micro light emitting diode Fig. 1: 112,
wherein each of the pixel areas Fig. 1: 110 is provided with at least one thin film transistor Fig. 1: T1 and at least one of the transfer units Fig. 1: 112+T2, and
an electron mobility of the second semiconductor pattern is at least five times an electron mobility of the first semiconductor pattern.
Kang discloses the following claim limitations not disclosed by Wang:
an electron mobility of the second semiconductor pattern is at least five times an electron mobility of the first semiconductor pattern (para. 0008).
Kang teaches the (“The amorphous silicon TFT has electrical charge mobility of about 0.5-1.0 cm^2/V-sec, and, therefore, it can be used as a switching element”; “To overcome this problem, a polycrystalline silicon TFT using polycrystalline silicon having electrical charge mobility of about 20-150 cm^2/V-sec as semiconductor pattern is developed”). The ranges taught in Kang can be applied to meet the 5x relationship between the electron mobility of the first and second semiconductor patterns as claimed in the current application.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the micro-LEDs of Kim with the electron mobility difference as described by Kang in order to create sufficient electrical charge mobility without increasing the size of the driving circuit (para. 0017).
Regarding claim 3, Wang teaches the micro light emitting diode panel according to claim 1, wherein the electrodes Fig. 7: S1/D1/G1 of each of the thin film transistors Fig. 7: T1 comprise a source Fig. 7: S1, a drain Fig. 7: D1, and a gate Fig. 7: G1, the source Fig. 7: S1 and the drain Fig. 7: D1 are electrically connected to the first semiconductor pattern, the signal lines comprise a plurality of scan lines Fig. 7: SL and a plurality of data lines Fig. 7: DL, the source Fig. 7: S1, the drain Fig. 7: D1, and the data lines Fig. 7: DL are a same film layer (shown in Fig. 7), and the gate Fig. 7: G1 and the scan lines Fig. 7: SL are a same film layer (shown in Fig. 7).
Regarding claim 4, Kang discloses the following claim limitations not disclosed by Wang:
wherein an electron mobility of the first semiconductor pattern of each of the thin
film transistors is less than or equal to 20 cm2/(V·s) (para. 0008; “The amorphous silicon TFT has electrical charge mobility of about 0.5-1.0 cm2/(V·s), and therefore, it can be used as a switching element).
The range taught in Kang can be applied to meet the less than or equal to 20 cm2/V·s as claimed in the current application.
Regarding claim 5, Kang discloses:
the micro light emitting diode panel according to claim 1:
wherein the transistor element Fig. 7: T2 of each of the transfer units Fig. 7: 112+T2 is configured to control a driving current flowing through the micro light emitting diode Fig. 7: 112 during a light emitting stage (para. 0042),
the circuit substrate Fig. 7: 120 has a plurality of pixel circuits disposed between the signal lines (para. 0006-0007), and each of the pixel circuits comprises:
a first bonding pad Fig. 7: PD/132 of the part of the bonding pads Fig. 7: PD/132,
wherein one of the transfer units Fig. 7: 112+T2 is electrically bonded to the first bonding pad Fig. 7: PD/132; and
a light emission control unit Fig. 1: 111 (para.0032), coupled to the transistor element Fig. 1: T2 of the one of the transfer units Fig. 7: 112+T2 via the first bonding pad (Fig. 1 shows light emission control unit comprises T1 and T2, which are connected via a bonding pad of the bonding layer 132), and
configured to conduct the driving current to the micro light emitting diode Fig. 7: 112 of the one of the transfer units Fig. 7: 112+T2 during the light emitting stage (para. 0038).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220068193) and Kang et al. (US 20090224262) as applied to claim 1 above, and further in view of Rovitto (2017).
Regarding claim 2, Rovitto discloses the following claim limitations not disclosed by Wang or Kang: the micro light emitting diode panel according to claim 1, further comprising:
a plurality of solder bumps, wherein the transfer units are electrically bonded to the circuit substrate via the solder bumps.
Wang teaches a bonding layer Fig. 7: 132 that includes bonding pads Fig. 7: PD where the transfer units are electrically bonded. Rovitto teaches, and it is also common in the art, where chip pads can be metallized on an IC, in a wafer processing step, and solder bumps are deposited on each of the chip pads, and also aligned to the bond pads on the substrate. Fig. 1: 9 shows this process.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention that the bonding layer Fig. 7: 132 and the bonding pads Fig. 7: PD of Wang’s invention also includes a solder bump according to Rovitto’s teachings, in order to provide electrically and thermally conductive paths to carry electrical current and heat from the chip to the substrate, guaranteeing mechanical support during the mounting of the die (or other elements) to the substrate (Rovitto, Section 1.3.2).
Claims 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20220068193) and Kang et al. (US 20090224262), as applied to claim 1 above, and further in view of Herner (US 20210305464).
Regarding claim 6, Herner discloses the following claim limitations not disclosed by Wang or Kang: the micro light emitting diode panel according to claim 5, further comprising:
a storage capacitor Fig. 5: 400S, electrically connected to the transistor element Fig. 5: 300 and the micro light emitting diode Fig. 5: 500 of the one of the transfer units Fig. 5: 300+500 (para. 0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Wang and Kang with Herner for the purpose of having a control apparatus to switch the LED on and off (para. 0003).
Regarding claim 7, Herner discloses the following claim limitations not disclosed by Wang or Kang: the micro light emitting diode panel according to claim 6,
wherein the storage capacitor Fig. 5: 400S is integrated in one of the transfer units Fig. 5: 300+500 (shown in Fig. 5).
Regarding claim 8, Wang discloses the micro light emitting diode panel according to claim 6, wherein each of the pixel circuits further comprises:
a second bonding pad Fig. 7: PD/132 of the part of the bonding pads Fig. 7: PD/132,
wherein the one of the transfer units Fig. 7: 112+T2 is further electrically connected to the second bonding pad Fig. 7: PD/132; and
a reset unit, coupled to the one of the transfer units via the second bonding pad,
wherein a gate of the transistor element of the one of the transfer units is coupled to the reset unit and a storage capacitor, and
the reset unit is configured to initialize a voltage of the storage capacitor during a reset stage.
Herner discloses the following claim limitations not disclosed by Wang or Kang:
a reset unit, coupled to the one of the transfer units Fig. 5: 300+500 (i.e. drive transistor/LED) via the second bonding pad Fig. 11C: 460 (of the LED of Fig. 5: 500),
wherein a gate of the transistor element Fig. 5: 300 of the one of the transfer units Fig. 5: 300+500 is coupled to the reset unit and a storage capacitor Fig. 5: 400S (para. 0003 also teaches capacitor connection to gate of drive transistor), and
the reset unit is configured to initialize a voltage of the storage capacitor Fig. 5: 400S during a reset stage (taught in para. 0003).
Herner teaches two transistors and a capacitor, one drive transistor and one address transistor, controlling the brightness of the LED and receiving scanning signals and an image data signal. Herner also teaches a source terminal connected to the gate of the drive transistor to control the on/off state of the drive transistor, and a capacitor also connected to the fate of the drive transistor helping in this operation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Wang and Kang with Herner for the purpose of having a control apparatus to switch the LED on and off (para. 0003).
Regarding claim 9, Wang discloses the micro light emitting diode panel according to claim 8, wherein each of the pixel circuits further comprises:
a third bonding pad of the part of the bonding pads,
wherein the one of the transfer units is further electrically connected to the third bonding pad
such that a cathode of the micro light emitting diode of the one of the transfer units is coupled to a system low voltage via the third bonding pad.
Herner discloses the following claim limitations not disclosed by Wang or Kang:
such that a cathode Fig. 11B: 530 (para. 0065) of the micro light emitting diode Fig. 5: 500 of the one of the transfer units Fig. 5: 300+500 is coupled to a system low voltage via the third bonding pad Fig. 16D: 160 (not labeled, but shown in Fig. 5).
Herner teaches bond pads are used to connect the LED contact (cathode) of the LED which is in operative communication with the transistor of the control apparatus (para. 0093, 0098), which his connected to a source terminal (system low voltage or VSS) taught in para. 0003.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Kang and Wang with Herner for the purpose of having a control apparatus to switch the LED on and off (para. 0003).
Regarding claim 10, Herner discloses the following claim limitations not disclosed by Kang or Wang: the micro light emitting diode panel according to claim 9:
wherein the transistor element Fig. 5: 300 of each of the transfer units Fig. 5: 300+500 is electrically connected between a corresponding micro light emitting diode Fig. 5: 500 and the circuit substrate Fig. 5: 100 in a thickness direction of the circuit substrate Fig. 5: 100, and
the third bonding pad Fig. 16D: 160 (not labeled, but shown in Fig. 5) is located on a side of the transistor element Fig. 5: 300 away from the corresponding micro light emitting diode Fig. 5: 500.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Wang and Kang with Herner in order to fit the control devices underneath the LED effectively reducing resistance losses that comes with short interconnection between the LED and the control devices (para. 0054).
Regarding claim 11, Herner discloses the following claim limitations not explicitly disclosed by Wang or Kang: the micro light emitting diode panel according to claim 8:
wherein the second bonding pad Fig. 11C: 460 of each of the pixel circuits (see Fig. 20A: 900) is coupled to the gate of the transistor element Fig. 5: 300 of the one of the transfer units Fig. 5: 300+500, the reset unit (as taught in claim 8 rejection above) and the storage capacitor Fig. 5: 400S, and
an image data is written into the storage capacitor during a data writing stage (para. 0003 teaches the control apparatus is designed to receive an image date signal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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