DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 7/10/26is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2010/0265749, hereinafter, Wang) in view of Kwon (US 2024/0312902.)
In regard to claim 1, in figs. 4A-4C, Wang discloses a semiconductor device comprising:
a substrate 440 (where the first transistor 420 formed, para [0056]).
a transistor 420 including a gate electrode 429 and a gate insulating layer stacked on the substrate and a junction 421 formed in the substrate (source/drain regions in a transistor inherently create a junction, or P/N junction);
a through via passing through the substrate through the junction and including a first portion that is in contact with the junction and a second portion extending from the first portion and having a width less than that of the first portion. Wang, however, does not show an insulating spacer surrounding the second portion of the through via.
Kwon, in figs. 6A-7B, discloses an analogous semiconductor device including transistors formed in a substrate 10 and further discloses connection vias labeled as element C in fig. 6B and detailed in figs. 7A-7B. Kwon further teaches an insulating spacer VSP surrounding the second portion of the through via V1, fig. 7A. This is common in the art since the insulation/barrier prevents diffusion and provides support and protection.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filling date of the application to form the via as taught in order to take the advantage.
Regarding claim 2, the above combination further comprising:
a memory cell array; and
a bonding structure bonding the memory cell array and the substrate,
wherein the memory cell array is electrically connected to the transistor through the through via. See Wang’s figs. 6-7 and Kwon’s figs. 1 and 6A.
Regarding claim 3, the combination further comprising: a first wafer including a peripheral circuit; and
a bonding structure bonding the first wafer and a second wafer including the substrate, the transistor, the through via, and the insulating spacer, wherein the peripheral circuit is electrically connected to the transistor through the through via. See Kwon’s figs. 5 and 6A.
Regarding claims 4-6, the combination further comprising: Kwon’s figs. 6A and 7B:
a first bonding layer 100;
at least one first bonding pad DSP in the first bonding layer;
a second bonding layer 260/250 bonded to the first bonding layer; and
at least one second bonding pad positioned in the second bonding layer and electrically connected to the at least one first bonding pad, wherein the through via is electrically connected to the at least one second bonding pad.
Regarding claims 7 and 13, the combination further discloses wherein the first portion has a hemispherical shape. See Wang’s fig. 4A and Kwon’s fig.6A.
Regarding claim 8, the combination comprising:
a first wafer including a first substrate and a first transistor;
a second wafer including a second substrate and a second transistor;
a memory cell array positioned between the first wafer and the second wafer; and
a through via passing through the second substrate through a junction of the second transistor and electrically connecting the second transistor and the memory cell array. See Kwon’s fig. 6A.
Regarding claim 9, Kwon further comprising: a first bonding structure positioned between the first wafer and 20 the memory cell array; and
a second bonding structure positioned between the second wafer and the memory cell array. Fig. 6A.
Regarding claims 10-11, as mentioned above, the combination discloses wherein the through
via is electrically connected to the memory cell array through a bonding pad in the second bonding structure.
Regarding claim 12, as mentioned in claim 1 above, wherein the through via includes a first portion that is in contact with the junction and a second portion extending from the first portion and having a width less than that of the first portion.
Regarding claim 14, as mentioned above (claim 1), further comprising: an insulating spacer surrounding the second portion of the through via.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814
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