DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/24/2024 was filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-11, 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al., U.S. Pub. No. 2021/0098421.
Regarding claim 1, Wu discloses (Fig. 1D):
a hybrid substrate, wherein the hybrid substrate comprising:
a first circuit substrate 110, having a first surface and a second surface,
a plurality of second circuit substrates (portion between layer 110 and 350, and layer 350) disposed on the first surface,
an interlayer 114, disposed between the plurality of second circuit substrates and the first circuit substrate, and
a plurality of electrical connection units 120 (Figs. 1C-1D), penetrating the plurality of second circuit substrates respectively, wherein at least one electrical connection unit among the plurality of electrical connection units comprises a through hole and a conductive material disposed in the through hole, and the at least one electrical connection unit is electrically connected to the first circuit substrate.
Regarding claim 2, Wu discloses wherein the interlayer (the top layer 114 that directly under the layer 140 and 120) combines and insulates the plurality of second circuit substrates and the first circuit substrate (Fig. 1D).
Regarding claim 3, Wu discloses a plurality of electronic components 150, 200A-200C and/or driver circuits disposed on third surfaces of the plurality of second circuit substrates (Fig. 1F)
Regarding claim 4, Wu discloses a molding layer 210, disposed on the electronic components and/or the driver circuits (Fig. 1F).
Regarding claim 6, Wu discloses wherein the plurality of electronic components are electrically connected to the first circuit substrate through the at least one electrical connection unit (Figs. 1C-1F).
Regarding claim 7, Wu discloses a plurality of driver circuits 300 (112) disposed on the second surface of the first circuit substrate (Fig. 1G).
Regarding claim 8, Wu discloses a plurality of electronic components disposed on third surfaces of the second substrates.
Regarding claim 9, Wu discloses a molding layer 210 disposed on the second substrates.
Regarding claim 10, Wu discloses wherein the plurality of second substrates comprise at least two second substrates, and the at least two second substrates are separated from each other (2 parts of two sides of chip 130, Fig. 1F).
Regarding claim 11, Wu discloses there is a gap between the two second substrates and exposes part of the interlayer (Fig. 1F, a die 130 is in between the 2 substrates).
Regarding claim 15, Wu discloses the first circuit substrate comprises a first pad and second circuit substrate comprise second pads and at least one electrical connection unit is electrically connected to the first pad and the second pad (Figs. 1C-1F).
Regarding claim 16, Wu discloses the second substrates are electrically connected to the first substrate through the pad, and connection unit (Fig. 1D).
Regarding claim 17, Wu discloses wherein at least one electrical connection unit overlaps the first pad and the second pad in a normal direction of the first circuit substrate (Fig. 1C).
Regarding claim 18, Wu discloses the plurality of electrical connection units (through hole) penetrate the second pad, the second substrates, and the interlayer (Fig. 1C).
Regarding claim 19, Wu discloses wherein the second substrates have a plurality of regions, electrical connections units disposed in the plurality of regions (Fig. 1D).
Regarding claim 20, Wu discloses (Fig. 1D):
a hybrid substrate, wherein the hybrid substrate comprising:
a first circuit substrate 110, having a first surface and a second surface,
a plurality of second circuit substrates (portion between layer 110 and 350, and layer 350) disposed on the first surface,
an interlayer 114, disposed between the plurality of second circuit substrates and the first circuit substrate, and
a plurality of electrical connection units 120 (Figs. 1C-1D), penetrating the plurality of second circuit substrates respectively, wherein at least one electrical connection unit among the plurality of electrical connection units comprises a through hole and a conductive material disposed in the through hole, and the at least one electrical connection unit is electrically connected to the first circuit substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., U.S. Pub. No. 2021/0098421.
Regarding claim 5, Wu discloses a pitch between two adjacent electronic components but fails to disclose the pitch is less than 1.5 mm. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942).
Regarding claims 12-14, Wu fails to disclose the size of line width and metal trances and the areas of the second circuit substrate and first circuit substrates. However, the selection of such parameters such as energy, concentration, temperature, time, molar fraction, depth, thickness, etc., would have been obvious and involve routine optimization which has been held to be within the level of ordinary skill in the art. "Normally, it is to be expected that a change in energy, concentration, temperature, time, molar fraction, depth, thickness, etc., or in conbination of the parameters would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art ... such ranges are termed "critical ranges and the applicant has the burden of proving such criticality.... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller 105 USPQ233, 255 (CCPA 1955). See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/THAO P LE/Primary Examiner, Art Unit 2818
Prosecution Insights