Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 of U.S. Application 18/644,834 filed on April 24, 2024 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/28/2024, 07/28/2024 and 06/02/2025 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show a signal splitter, a delay element, a comparison circuit, and a controller as described in the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-7, 9, 12, 14,16-18, and 20 are rejected under 35 U.S.C. 102(a1) as being unpatentable over Landman et al (USPGPub 20200393506).
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Prior art: Landman
Regarding claim 1, Landman discloses sensor (shown in figs 1-11) for measuring a specific logic circuitry (par 52 discloses IC margin measurement) of a semiconductor Integrated Circuit (IC), comprising: a signal splitter (similar to 1) configured to split a signal from the specific logic circuitry into two test paths (par 63 discloses splitting into two signals); a delay element, configured to receive and apply a delay (such as 2) to a first of the two test paths (par 63 discloses applying delay to one of two signal paths), the delay being based on a predetermined timing margin that is selected from a group of discrete timing margin values (par 63 discloses measurement time margins), the group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value (pars 71, 84, and 141 discloses minimum vs maximum margin); a comparison circuit (such as 3) configured to compare the delayed first test path and a second of the two test paths and provide a measurement output according to the comparison for an instance of measuring (par 64 discloses a comparison circuit to compare the delayed signal and combiner output); and a controller (such as 101A which is already a computer but also shown as annotated 4), configured to set the predetermined timing margin such that, over a plurality of the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each of the at least one longer timing margin value (par 72 discloses measuring minimum delay margin and par 141 discloses rates over times and minimum and max values. Therefore, based on intended values, the frequency of the shorter values is greater than the longer).
Regarding claim 2, Landman discloses wherein the sensor is configured to complete each of the plurality of instances of measuring over a same number of clock cycles of the semiconductor IC (par 92 discloses can be on the same clock cycle).
Regarding claim 3, Landman discloses wherein the controller is configured to select the respective predetermined timing margin for each measuring over successive instances of the plurality of instances from the group of discrete timing margin values according to a predetermined sequence, the predetermined sequence being defined such that the frequency of selection of the shortest timing margin value is higher than the frequency of selection of each of the at least one longer timing margin value (par 49 and 66 discloses repeating over different times. Therefore, it is successive instances. Par 72 discloses measuring minimum delay margin and par 141 discloses rates over times and minimum and max values. Therefore, based on intended values, the frequency of the shorter values is greater than the longer
Regarding claim 4, Landman discloses wherein the predetermined sequence repeats each predefined number of instances (par 49 and 66 discloses repeating over different times. Therefore, it repeats each predefined number of instances).
Regarding claim 5, Landman discloses wherein the sensor is local to the specific logic circuitry (shown in figs 1-4 as being local to the logic circuitry).
Regarding claim 6, Landman discloses wherein the comparison circuit comprises a logic gate configured to receive a signal from the delayed first test path and a signal from the second test path as inputs (claim 19 discloses using an OR gate to receive the first comparison and second comparison parts).
Regarding claim 7, Landman discloses wherein the group of discrete timing margin values comprises a shortest timing margin value and a plurality of longer timing margin values (par 17 discloses between at least 1 and 100,000 from the clock period so there is a shortest and longest values).
Regarding claim 9, Landman discloses wherein for each of the plurality of longer timing margin values, a frequency of selection of the respective timing margin value is higher than a frequency of selection of each timing margin value longer than the respective timing margin value (shown in pars 72 and 143 discloses smallest margin and having a max values which is increased by a margin. Therefore, a frequency of selection is higher than a frequency of selection based on timing margin values).
Regarding claim 12, Landman discloses wherein the measuring is performed on a combined data path signal comprising a combination of individual data path signals, each of the individual data path signals coming from a different part of the specific logic circuitry (shown in figs 1-5 as an individual data path).
Regarding claim 14, Landman discloses comprising: a signal path combiner, configured to combine signals from multiple data paths of the specific logic circuitry (using combinatoric logic); and wherein the signal from the specific logic circuitry provided to the signal splitter comprises the combined signals (shown in figs 1-4 as logic to combine the values).
Regarding claim 16, Landman discloses a system (shown in figs 1-11) for measuring a semiconductor integrated circuit (IC), the system comprising: a functional circuit of the semiconductor IC (par 52 discloses IC margin measurement), comprising logic circuitry (shown in figs 1-4); and a sensor (par 63 discloses a circuit which may be a detector) on the semiconductor IC, associated with the functional circuit and configured to receive a signal from one or more data paths of the logic circuitry (shown in at least fig 1), the sensor comprising: a signal splitter (similar to 1) configured to split a signal from the specific logic circuitry into two test paths (par 63 discloses splitting into two signals); a delay element, configured to receive and apply a delay (such as 2) to a first of the two test paths (par 63 discloses applying delay to one of two signal paths), the delay being based on a predetermined timing margin that is selected from a group of discrete timing margin values (par 63 discloses measurement time margins), the group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value (pars 71, 84, and 141 discloses minimum vs maximum margin); a comparison circuit (such as 3) configured to compare the delayed first test path and a second of the two test paths and provide a measurement output according to the comparison for an instance of measuring (par 64 discloses a comparison circuit to compare the delayed signal and combiner output); and wherein the system(such as 101A which is already a computer but also shown as annotated 4),is configured to set the predetermined timing margin such that, over a plurality of the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each of the at least one longer timing margin value (par 72 discloses measuring minimum delay margin and par 141 discloses rates over times and minimum and max values. Therefore, based on intended values, the frequency of the shorter values is greater than the longer).
Regarding claim 17, Landman discloses wherein the system is configured to set the predetermined timing margin using a controller on the semiconductor IC and/or an interface external the semiconductor IC (par 79 discloses timing margin are provided at the beginning of the circuitry and fig 1 discloses a Pc. Therefore, the Pc an external interface the semiconductor).
Regarding claim 18, Landman discloses wherein the system is further configured to determine a timing margin of the functional circuit based on the plurality of instances of the measurement and to set a clock of the semiconductor IC based on the determined timing margin (par 68 discloses timing margin based on clock signal. Therefore, the system is able to determine timing margin and set clock data).
Regarding claim 20, Landman discloses a non-transitory computer readable medium (pars 81discloses non-transitory storage) having stored thereon a computer-readable encoding (par 152 discloses encoding) of a sensor (par 63 discloses having a detector) for measurement in a semiconductor Integrated Circuit (IC) (150), the computer-readable encoding of the sensor comprising encodings of: a signal splitter (similar to 1) configured to split a signal from the specific logic circuitry into two test paths (par 63 discloses splitting into two signals); a delay element, configured to receive and apply a delay (such as 2) to a first of the two test paths (par 63 discloses applying delay to one of two signal paths), the delay being based on a predetermined timing margin that is selected from a group of discrete timing margin values (par 63 discloses measurement time margins), the group of discrete timing margin values comprising a shortest timing margin value and at least one longer timing margin value (pars 71, 84, and 141 discloses minimum vs maximum margin); a comparison circuit (such as 3) configured to compare the delayed first test path and a second of the two test paths and provide a measurement output according to the comparison for an instance of measuring (par 64 discloses a comparison circuit to compare the delayed signal and combiner output); and a controller (such as 101A which is already a computer but also shown as annotated 4), configured to set the predetermined timing margin such that, over a plurality of the instances of measuring, a frequency of selection of the shortest timing margin value is higher than a frequency of selection of each of the at least one longer timing margin value (par 72 discloses measuring minimum delay margin and par 141 discloses rates over times and minimum and max values. Therefore, based on intended values, the frequency of the shorter values is greater than the longer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Landman et al (USPGPub 20200393506) in view of Atsatt et al (USPGPub 20190095564).
Reagrding claim 19, Landman does not fully disclose wherein the system is configured to set the clock of the semiconductor IC and/or the voltage of the semiconductor IC using one or more of: an Automatic Voltage Scaling (AVS) mechanism; an Automatic Frequency Scaling mechanism (AFS) and a Dynamic Voltage and Frequency Scaling (DVFS) mechanism.
However, Atsatt discloses wherein the system is configured to set the clock of the semiconductor IC and/or the voltage of the semiconductor IC using one or more of a Dynamic Voltage and Frequency Scaling (DVFS) mechanism (par 35 discloses DVFS). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Landman in view of Atsatt because it is known to adjust clock for calibration (Atsatt par 32).
Allowable Subject Matter
Claims 8, 10, 11, 13, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the prior art of record taken alone or in combination fail to teach or suggest a sensor for measuring a specific logic circuitry of a semiconductor Integrated Circuit (IC), comprising: wherein the frequency of selection of the shortest timing margin value is at least a sum of frequencies of selection of each of the plurality of longer timing margin values in combination with the other limitations of the claim.
Regarding claim 10, the prior art of record taken alone or in combination fail to teach or suggest a sensor for measuring a specific logic circuitry of a semiconductor Integrated Circuit (IC), comprising: wherein for each of the plurality of longer timing margin values, the ratio of the frequency of selection of the shortest timing margin value to the frequency of selection of the respective longer timing margin value is inversely proportional to the ratio of the shortest timing margin value to the respective longer timing margin value in combination with the other limitations of the claim.
Regarding claim 11, the prior art of record taken alone or in combination fail to teach or suggest a sensor for measuring a specific logic circuitry of a semiconductor Integrated Circuit (IC), comprising: wherein the plurality of longer timing margin values are defined as a sequence, each longer timing margin value in the sequence being double a preceding longer timing margin value in the sequence in combination with the other limitations of the claim.
Regarding claim 13, the prior art of record taken alone or in combination fail to teach or suggest a sensor for measuring a specific logic circuitry of a semiconductor Integrated Circuit (IC), comprising: wherein each instance of the measuring determines if a failure condition is met for the respective predetermined timing margin, the controller being further configured to output an indication of a maximum timing margin for which the failure condition is not met and/or a minimum timing margin for which the failure condition is met, based on the determinations for the plurality of instances of the measuring in combination with the other limitations of the claim.
Regarding claim 15, the prior art of record taken alone or in combination fail to teach or suggest a sensor for measuring a specific logic circuitry of a semiconductor Integrated Circuit (IC), comprising: wherein the controller is configured to set the predetermined timing margin so as to apply varying delay to the signal passing through the first test path over different instances of the measurement and to determine a worst-case remaining margin of the multiple data paths, based on the comparison of the first and second test paths in combination with the other limitations of the claim.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al (USPGPub 20180122666): discloses test system with a plurality of DUTs.
Atkinson et al (USPGpub 20170093399): discloses high speed with low voltage comparator.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST.
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/DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858