Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
3 pending office actions • 1 art units • 3 examiners • 0 of 3 (0%) have an AI response strategy ready • 6 patents granted in the last 365 days
Proteantecs Ltd. currently manages 3 pending office actions within the Semiconductors, Circuits & Optics technology area. These actions are distributed across 3 distinct examiners, indicating that each pending matter is handled by a different individual. The portfolio involves 1 distinct art unit, suggesting a unified technical classification for these filings.
ASTACIO-OQUENDO, GIOVANNI is identified as the busiest examiner for the company, currently overseeing 1 pending office action. This examiner is one of the 3 distinct examiners engaged with the portfolio. The 3 pending office actions are concentrated within 1 distinct art unit, which may streamline the prosecution strategy within Semiconductors, Circuits & Optics.
The involvement of 3 distinct examiners for 3 pending office actions means there is no overlap in personnel across the current cases. ASTACIO-OQUENDO, GIOVANNI handles 1 pending office action, while the other actions are assigned elsewhere. Practitioners can focus their analysis on the 1 distinct art unit to understand the specific standards applied to the company's Semiconductors, Circuits & Optics applications.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 only | 1 (33%) |
| §101 + other | 1 (33%) |
| Multi-statute (no §101) | 1 (33%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| ASTACIO-OQUENDO, GIOVANNI | 1 | 88.5% | +10.4% |
| JAGAN, MIRELLYS | 1 | 82.9% | +5.7% |
| BHAT, ADITYA S | 1 | 81.1% | +10.0% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18817199 | INTEGRATED CIRCUIT WORKLOAD, TEMPERATURE, AND/OR SUB-THRESHOLD LEAKAGE SENSOR | ASTACIO-OQUENDO, GIOVANNI | — |
| 18833051 | THERMAL SENSOR FOR INTEGRATED CIRCUIT | JAGAN, MIRELLYS | — |
| 18685070 | INTEGRATED CIRCUIT DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION USING WORKLOAD AND MARGIN SENSING | BHAT, ADITYA S | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18817199 | INTEGRATED CIRCUIT WORKLOAD, TEMPERATURE, AND/OR SUB-THRESHOLD LEAKAGE SENSOR | ASTACIO-OQUENDO, GIOVANNI | — |
| 18685070 | INTEGRATED CIRCUIT DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION USING WORKLOAD AND MARGIN SENSING | BHAT, ADITYA S | — |
| Art Unit | Apps |
|---|---|
| 2858 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18817199 | INTEGRATED CIRCUIT WORKLOAD, TEMPERATURE, AND/OR SUB-THRESHOLD LEAKAGE SENSOR | ASTACIO-OQUENDO, GIOVANNI | 2858 | §101 | Non-Final OA | — | Pending | Aug 27, 2024 |
| 18833051 | THERMAL SENSOR FOR INTEGRATED CIRCUIT | JAGAN, MIRELLYS | — | §102§103 | Non-Final OA | — | Pending | Jul 25, 2024 |
| 18685070 | INTEGRATED CIRCUIT DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION USING WORKLOAD AND MARGIN SENSING | BHAT, ADITYA S | — | §101§102 | Non-Final OA | — | Pending | Feb 20, 2024 |
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