Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Examiner cites particular columns or paragraphs, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In reply to the Final Office Action mailed on 12/2/2025, the Applicant has filed a Request for Continued Examination on 2/23/2026 amending claims 1, 11, 15 and 18. No claim has been added or cancelled. Claims 1-20 are pending in this application.
Previous rejections under the first paragraph of 35 U.S.C. 112(a) are withdrawn in view of applicant’s amendments filed on 2/23/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 13 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jiang et al. (US 2021/0241685).
Regarding claim 11, Jiang discloses a display panel driving device (para[0051]; para[0075]; para[0134]; see drive device 00 for a display panel 01 in Fig. 9), comprising:
a digital circuit unit (para[0091]; see digital circuit 201 in Figs. 2 and 9); and
a power management integrated circuit (PMIC) (para[0051]-para[0052]; para[0093]; power management integrated circuit 100 in Figs. 2 and 9),
wherein the digital circuit unit is supplied with
an internal power supply voltage during driving of a display panel (para[0052]; para[0054]; para[0067]; para[0071]-para[0075]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is supplied with “a first power supply voltage” (taken as the claimed internal power supply voltage) at the digital power supply terminal DVDD by power management circuit 100, to drive display panel 10 to display colored or white pictures; “the power supply from the drive device provided in the embodiments… refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”), and is further supplied with hat is adjusted a load mode of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0075]; para[0085]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is further supplied with “a second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; the power management circuit 100 supplies voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, to display e.g. colored pictures; “the power supply from the drive device provided in the embodiments of the present disclosure refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”, and the external power supply voltage at power supply terminal VDD is provided through the internal driver circuit 200 “to the digital power supply terminal DVDD when the voltage of the digital power supply terminal DVDD is lower than the reference voltage” during a high load mode/current and is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current).
Regarding claim 13, Jiang discloses all the claim limitations as applied above (see claim 11). In addition, Jiang discloses the load mode comprises a light mode (e.g. “the load current is small when the white picture is displayed”; para[0101]) and a heavy mode (e.g. “the load current is large when the display panel displays the color picture”; para[0104]), and
wherein an amount of IR voltage drop varies depending on the load mode of the digital circuit unit (para[0071]; para[0073]; e.g. “when displaying a color picture, the load current of the display panel is generally 100-200 milliamperes (mA)”, and “a resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is large”; “when displaying a white picture with a grayscale of 255, the load current of the display panel is generally 50-70 mA”, and “when the power management circuit 100 provides the first power supply voltage to the digital power supply terminal DVDD, the resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is small”), and the external power supply voltage adjusted by the amount of the IR voltage drop is supplied to the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0074]; para[0085]; para[0091]; para[0099]-para[0108]; see Fig. 9; as discussed above, digital circuit 201 is further supplied with the “second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; that is, the “second power supply voltage provided by a power supply terminal VDD” is adjusted according to whether the load current is small (e.g. when the white picture is displayed), or the load current is large (e.g. when the display panel displays the color picture), and thus by the corresponding voltage drop (IR Drop)).
Regarding claim 18, Jiang discloses a method of driving a display panel in a display panel driving device configured to control driving of the display panel, the method comprising:
transmitting and receiving, by a power management integrated circuit (PMIC), load mode information of a digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0075]; para[0085]; para[0091]; para[0099]-para[0100]; para[0104]; para[0106]-para[0107]; para[0134]; Figs. 2 and 9; “The digital circuit 201 is configured to provide a drive voltage to the display panel under the drive of the digital power supply terminal DVDD”; “when the voltage of the digital power supply terminal DVDD is lower than the reference voltage, the power management circuit 100 and the internal driver circuit 200 may jointly supply power to the digital power supply terminal DVDD” (heavy load); “When the voltage of the digital power supply terminal DVDD is not lower than the reference voltage, the power management circuit 100 may separately supply power to the digital power supply terminal DVDD” (light load); thus, the digital circuit 201 providing the load condition/mode to the power management circuit 100); and
adjusting, by the PMIC, an external power supply voltage according to a load mode of the digital circuit unit, and supplying the adjusted external power supply voltage to the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0099]-para[0100]; para[0104]; para[0106]-para[0107]; para[0134]; Figs. 2 and 9; see the digital circuit 201 is supplied with “a second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; as discussed above, when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, the power management circuit 100 controls voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way, according to the load mode/current, e.g. during a high load mode/current; the external power supply voltage is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current); and
supplying, to the digital circuit unit, during driving of the display panel para[0052]; para[0054]; para[0067]; para[0071]-para[0075]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is supplied with “a first power supply voltage” (taken as the claimed internal power supply voltage) at the digital power supply terminal DVDD by power management circuit 100, to drive display panel 10 to display colored or white pictures; “the power supply from the drive device provided in the embodiments… refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”).
Regarding claim 19, Jiang discloses all the claim limitations as applied above (see claim 18). In addition, Jiang discloses when a load current of the digital circuit unit increases, the external power supply voltage is adjusted to be greater than or equal to a minimum operating voltage (VDD min) that ensures operation of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0072]; para[0104]; the “second power supply voltage provided by a power supply terminal VDD” (claimed external power supply voltage) is converted and adjusted into the third power supply voltage by the internal driver circuit 200 “when the load current of the display panel is so large that the voltage of the digital power supply terminal DVDD is not greater than the reference voltage”, and “the internal driver circuit 200 and the power management circuit 100 may supply power to the digital power supply terminal DVDD simultaneously”, “to ensure that the voltage of the digital power supply terminal DVDD is greater than or equal to the reference voltage”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147).
Regarding claim 1, Jiang discloses a display panel driving device (para[0051]; para[0134]; see drive device 00 for a display panel 01 in Fig. 9), comprising:
a power management integrated circuit (PMIC) (para[0051]-para[0052]; para[0093]; power management integrated circuit 100 in Figs. 2 and 9); and
a digital circuit unit configured to drive a display panel (para[0091]; see digital circuit 201 in Figs. 2 and 9),
wherein the digital circuit unit is supplied with during driving of the display panel (para[0052]; para[0054]; para[0067]; para[0071]-para[0075]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is supplied with “a first power supply voltage” (taken as the claimed internal power supply voltage) at the digital power supply terminal DVDD by power management circuit 100, to drive display panel 10 to display colored or white pictures; “the power supply from the drive device provided in the embodiments… refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”), and is further supplied with a load mode of the digital circuit unit, thereby controlling the driving of the display panel (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0075]; para[0085]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is further supplied with “a second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; the power management circuit 100 supplies voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, to drive display panel 10 to display e.g. colored pictures; “the power supply from the drive device provided in the embodiments of the present disclosure refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”, and the external power supply voltage at power supply terminal VDD is provided through the internal driver circuit 200 “to the digital power supply terminal DVDD when the voltage of the digital power supply terminal DVDD is lower than the reference voltage” during a high load mode/current and is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current), and
controlling the PMIC based on the load mode, and enabling the external power supply voltage to be variably supplied to the digital circuit (para[0053]-para[0054]; para[0066]-para[0067]; para[0099]-para[0100]; para[0104]; para[0106]-para[0107]; para[0134]; Figs. 2 and 9; see the digital circuit 201 is supplied with “a second power supply voltage provided by a power supply terminal VDD” (claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; as discussed above, when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, the power management circuit 100 is controlled to provide voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way, according to the load mode/current, e.g. during a high load mode/current; the external power supply voltage is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current).
However, Jiang does not appear to expressly disclose a control integrated circuit (IC); wherein the control IC is configured to control the PMIC based on the load mode,
Chen discloses a control integrated circuit (IC) (see circuit 330 in Fig. 3; column 8 lines 52-53); wherein the control IC is configured to control a PMIC according to a load mode and enable an external power supply voltage to be variably supplied to a digital circuit unit according to the control operation of the control IC (regarding Fig. 3, circuit 330 controls power IC 340 according to a load mode and enables voltage supply to display IC 350, accordingly; “The compensation power circuit 330 generates a control signal 326 to adjust the input voltage to the display IC 350 to account for a voltage drop between the power IC 340 and the display IC 350 based on the load signal 314 from the load estimation circuit 320 of the GPU 234”; “The compensation power circuit 330 increases its output voltage so that the input voltage to the display IC 350 is increased when current between the power IC 340 and display IC 350 is increased (i.e., the load signal 314 indicates a high value), and decreases its output voltage so that the input voltage to the display IC 350 is increased when the current between the power IC 340 and display IC 350 is decreased (i.e., the load signal 314 indicates a low value)”, its output voltage being external to the voltage from the power IC 340; column 8 lines 3-15 and 36-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s invention, with the teachings in Chen’s invention, to have a control integrated circuit (IC), wherein the control IC is configured to control the PMIC according to the load mode and enable the external power supply voltage to be variably supplied to the digital circuit unit according to the control operation of the control IC, for the advantage of an alternative configuration to ensure voltage at the digital circuit is maintained relatively constant even when its current load fluctuates (column 8 lines 3-18 and 36-55).
Regarding claim 2, Jiang and Chen disclose all the claim limitations as applied above (see claim 1). In addition, Jiang discloses the load mode comprises a light mode (e.g. “the load current is small when the white picture is displayed”; para[0101]) and a heavy mode (e.g. “the load current is large when the display panel displays the color picture”; para[0104]), and
wherein an amount of IR voltage drop varies depending on the load mode (para[0071]; para[0073]; e.g. “when displaying a color picture, the load current of the display panel is generally 100-200 milliamperes (mA)”, and “a resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is large”; “when displaying a white picture with a grayscale of 255, the load current of the display panel is generally 50-70 mA”, and “when the power management circuit 100 provides the first power supply voltage to the digital power supply terminal DVDD, the resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is small”), and the adjusted external power supply voltage by the amount of IR voltage drop is supplied (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0074]; para[0085]; para[0091]; para[0099]-para[0108]; see Fig. 9; as discussed above, digital circuit 201 is further supplied with the “second power supply voltage provided by a power supply terminal VDD” (the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; that is, the “second power supply voltage provided by a power supply terminal VDD” is adjusted according to whether the load current is small (e.g. when the white picture is displayed), or the load current is large (e.g. when the display panel displays the color picture), and thus by the corresponding voltage drop (IR Drop)).
Regarding claim 3, Jiang and Chen disclose all the claim limitations as applied above (see claim 2). In addition, Jiang discloses in the heavy mode, the digital circuit unit is supplied with the adjusted external power supply voltage to be greater than or equal to a minimum operating voltage (VDD min) that ensures operation of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0072]; para[0104]; the “second power supply voltage provided by a power supply terminal VDD” (the claimed external power supply voltage) is converted and adjusted into the third power supply voltage by the internal driver circuit 200 “when the load current of the display panel is so large that the voltage of the digital power supply terminal DVDD is not greater than the reference voltage”, and “the internal driver circuit 200 and the power management circuit 100 may supply power to the digital power supply terminal DVDD simultaneously”, “to ensure that the voltage of the digital power supply terminal DVDD is greater than or equal to the reference voltage”), and
wherein the heavy mode is a mode where a load current is highest (e.g. “When the color of a picture displayed by the display panel is complicated”, and “the load current of the display panel is so large that the voltage of the digital power supply terminal DVDD is not greater than the reference voltage”; para[0071]-para[0072]; para[0104]).
Regarding claim 5, Jiang and Chen disclose all the claim limitations as applied above (see claim 1). In addition, Jiang discloses the external power supply voltage is adjusted by an amount of IR voltage drop to be supplied to the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0074]; para[0085]; para[0091]; para[0099]-para[0108]; see Fig. 9; e.g. “when displaying a color picture, the load current of the display panel is generally 100-200 milliamperes (mA)”, and “a resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is large”; “when displaying a white picture with a grayscale of 255, the load current of the display panel is generally 50-70 mA”, and “when the power management circuit 100 provides the first power supply voltage to the digital power supply terminal DVDD, the resistance voltage drop (IR Drop) caused by the line impedance between the power management circuit 100 and the digital power supply terminal DVDD is small”; accordingly, the digital circuit 201 is supplied with the “second power supply voltage provided by a power supply terminal VDD” (the claimed external power supply voltage), converted and adjusted into the third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; that is, the “second power supply voltage provided by a power supply terminal VDD” is adjusted according to whether the load current is small (e.g. when the white picture is displayed), or the load current is large (e.g. when the display panel displays the color picture), and thus by the corresponding voltage drop (IR Drop)).
Regarding claim 12, Jiang discloses all the claim limitations as applied above (see claim 11). In addition, Jiang discloses wherein the digital circuit unit is configured to transmit load mode information to the PMIC (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0075]; para[0085]; para[0091]; para[0099]-para[0100]; para[0104]; para[0106]-para[0107]; para[0134]; Figs. 2 and 9; “The digital circuit 201 is configured to provide a drive voltage to the display panel under the drive of the digital power supply terminal DVDD”; “when the voltage of the digital power supply terminal DVDD is lower than the reference voltage, the power management circuit 100 and the internal driver circuit 200 may jointly supply power to the digital power supply terminal DVDD” (heavy load); “When the voltage of the digital power supply terminal DVDD is not lower than the reference voltage, the power management circuit 100 may separately supply power to the digital power supply terminal DVDD” (light load); thus, the digital circuit 201 providing the load condition/mode to the power management circuit 100), and
wherein the PMIC is configured to control the external power supply voltage to be variably supplied to the digital circuit unit depending on the load mode (para[0053]-para[0054]; para[0066]-para[0067]; para[0099]-para[0100]; para[0104]; para[0106]-para[0107]; para[0134]; Figs. 2 and 9; see the digital circuit 201 is supplied with “a second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; as discussed above, when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, the power management circuit 100 controls voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way, according to the load mode/current, e.g. during a high load mode/current; the external power supply voltage is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current).
However, Jiang does not appear to expressly discloses a control integrated circuit (IC), wherein the digital circuit unit is configured to transmit load mode information to the PMIC upon request from the control IC.
Chen discloses a control IC (see circuit 330 in Fig. 3; column 8 lines 52-53), and transmitting load mode information upon request from the control IC (regarding Fig. 3, “The GPU 234… generates and provides a load signal 314 indicating expected power consumption for displaying the images output to the display device 32”; specifically, “The load estimation circuit 320… generates a load signal 314 representing power estimated for displaying the processed images” (“a load signal 314 set at a high level indicates heavy loading and a load signal set at a low level indicates light loading”), and “The compensation power circuit 330 generates a control signal 326 to adjust the input voltage to the display IC 350 to account for a voltage drop between the power IC 340 and the display IC 350 based on the load signal 314 from the load estimation circuit 320 of the GPU 234”; column 7, lines 27-57; column 8, lines 3-7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s invention, with the teachings in Chen’s invention, to have a control IC, wherein the digital circuit unit is configured to transmit load mode information to the PMIC upon request from the control IC, for the advantage of an alternative configuration that ensures voltage at the digital circuit is maintained relatively constant even when its current load fluctuates (column 8 lines 3-18 and 36-55).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147), as applied to claim 2 above, and further in view of Yang et al. (US 2017/0069251).
Regarding claim 4, Jiang and Chen disclose all the claim limitations as applied above (see claim 2). In addition, Jiang discloses the light mode has a lower load current than the heavy mode (para[0071]-para[0074]; para[0099]-para[0101]; para[0104]; “When the color of the picture displayed by the display panel is relatively single” or white, “the load current of the display panel is small”, and is smaller than “when the color of a picture displayed by the display panel is complicated”, during which “the load current of the display panel is so large”).
However, Jiang and Chen do not appear to expressly disclose in the light mode, the digital circuit unit is supplied with the adjusted external power supply voltage which does not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit.
Yang discloses in a light mode, a digital circuit unit is supplied with an adjusted external power supply voltage which does not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit (para[0106]-para[0107]; para[0128]; para[0131]; e.g., by calculating and using “analog power supply voltage of the source driver chip according to the brightness value required actually” for maximum brightness per sub-pixel (claimed light mode), “lower than the voltage corresponding to the maximum brightness”, “the power consumption of the source driver chip may be reduced and… the service life of the source driver chip is thereby prolonged”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang and Chen’s invention, with the teachings in Yang’s invention, to have in the light mode, the digital circuit unit is supplied with the adjusted external power supply voltage which does not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit, for the advantage of prolonging the service life of the circuit unit by reducing its power consumption (para[0047]).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147), as applied to claim 1 above, and further in view of Pyeon (US 2016/0111042).
Regarding claim 6, Jiang and Chen disclose all the claim limitations as applied above (see claim 1). In addition, Jiang discloses the PMIC mounted on a printed circuit board (PCB) (para[0095]; para[0134]; see in Fig. 9 “The power management circuit 100 is disposed on the PCB 001”).
However, Jiang and Chen do not appear to expressly disclose the control IC mounted on the printed circuit board (PCB).
Pyeon discloses a control IC and a PMIC are mounted on a printed circuit board (PCB) (regarding Figs. 1 and 9, “the timing controller 140 may be located on a control printed circuit board 160”, and “The control printed circuit board 160 may further include the power management integrated circuit (PMIC, not shown)”) para[0045]-para[0046]and [0151-0154].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s and Chen’s combination, with the teachings in Pyeon’s invention, to have the control IC and the PMIC are mounted on a printed circuit board (PCB), for the advantage of improved signal integrity and compact design.
Regarding claim 7, Jiang, Chen and Pyeon disclose all the claim limitations as applied above (see claim 6). In addition, Jiang discloses the PCB and the digital circuit unit are connected by a packaging type (see PCB 001 and digital circuit 201 connected by chip on film (COF) packaging 002 in Fig. 9; para[0094]-para[0095]; para[0134]).
Regarding claim 8, Jiang, Chen and Pyeon disclose all the claim limitations as applied above (see claim 7). In addition, Jiang discloses the packaging type is one of chip on film (COF) (see chip on film (COF) 002 in Fig. 9; para[0094]-para[0095]; para[0134]), chip on glass (COG), or chip on plastic (COP).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147), as applied to claim 1 above, and further in view of Lee (US 2019/0263339), hereinafter Lee ‘339.
Regarding claim 9, Jiang and Chen disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses an interface unit configured to connect the control IC and the digital circuit unit (see e.g. GPU 234 connecting circuit 330 and display IC 350, as shown in Fig. 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have an interface unit configured to connect the control IC and the digital circuit unit, for the advantage of efficiently processing signals in determining load signals (column 7, lines 27-50).
However, Jiang and Chen do not appear to expressly disclose the interface unit is configured to support a digital communication method and an analog communication method.
Lee ‘339 discloses an interface unit configured to support a digital communication method and an analog communication method (para[0007]; “interface circuit communicates utilizing an analog signal, an inter-integrated circuit (I2C) protocol, a serial peripheral interface bus protocol (SPI), or data packet”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s and Chen’s combination, with the teachings in Lee’s invention, to have the interface unit is configured to support a digital communication method and an analog communication method, for the advantage of increased versatility by using readily available and common standard alternative communication interfaces (para[0007]).
Claims 10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147), and further in view of Lee et al. (US 2016/0155374), hereinafter Lee ‘374.
Regarding claim 10, Jiang and Chen disclose all the claim limitations as applied above (see claim 1). In addition, Chen discloses transmitting load mode information to the control IC upon request from the control IC (regarding Fig. 3, “The GPU 234… generates and provides a load signal 314 indicating expected power consumption for displaying the images output to the display device 325”; specifically, “The load estimation circuit 320… generates a load signal 314 representing power estimated for displaying the processed images” (“a load signal 314 set at a high level indicates heavy loading and a load signal set at a low level indicates light loading”), and “The compensation power circuit 330 generates a control signal 326 to adjust the input voltage to the display IC 350 to account for a voltage drop between the power IC 340 and the display IC 350 based on the load signal 314 from the load estimation circuit 320 of the GPU 234”; column 7, lines 27-57; column 8, lines 3-7), and
wherein the control IC is configured to control the PMIC according to the load mode and enable the external power supply voltage to be variably supplied to the digital circuit unit (regarding Fig. 3, circuit 330 controls power IC 340 according to a load mode and enables voltage supply to display IC 350, accordingly; “The compensation power circuit 330 generates a control signal 326 to adjust the input voltage to the display IC 350 to account for a voltage drop between the power IC 340 and the display IC 350 based on the load signal 314 from the load estimation circuit 320 of the GPU 234”; “The compensation power circuit 330 increases its output voltage so that the input voltage to the display IC 350 is increased when current between the power IC 340 and display IC 350 is increased (i.e., the load signal 314 indicates a high value), and decreases its output voltage so that the input voltage to the display IC 350 is increased when the current between the power IC 340 and display IC 350 is decreased (i.e., the load signal 314 indicates a low value)”; column 8 lines 3-15 and 36-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to transmit load mode information to the control IC upon request from the control IC, and have the control IC is configured to control the PMIC according to the load mode and enable the external power supply voltage to be variably supplied to the digital circuit unit, as also taught by Chen in the combination, for the advantage of a configuration that ensures voltage at the digital circuit is maintained relatively constant even when its current load fluctuates (column 8 lines 3-18 and 36-55).
However, Jiang and Chen do not appear to expressly disclose the digital circuit unit is configured to transmit load mode information to the control IC upon request from the control IC.
Lee ‘374 discloses a digital circuit unit configured to transmit load mode information to a controller (para[0011]; para[0042]; para[0049]-[0051]; para[0053]; para[0060]; see in Fig. 5 sensing unit included in circuit 150 transmits digital load current/intensity C_load to controller 120).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s and Chen’s combination, with the teachings in Lee ‘374’s invention, to have the digital circuit unit is configured to transmit load mode information to the control IC upon request from the control IC, for the advantage of preventing unnecessary power consumption by using a design that senses load current in real time (para[0059]; para[0067]-para[0068]).
Regarding claim 15, it is analogous to claim 10, except it is a method claim (see para[0002] of Jiang; Fig. 4 of Chen, and para[0026], para[0060] of Lee ‘374), and therefore it is rejected for the same reasons as claim 10 above.
Regarding claim 16, Jiang, Chen and Lee ‘374 disclose all the claim limitations as applied above (see claim 15). In addition, Jiang discloses when a load current of the digital circuit unit increases, the external power supply voltage is adjusted to be greater than or equal to a minimum operating voltage (VDD min) that ensures operation of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0072]; para[0104]; the “second power supply voltage provided by a power supply terminal VDD” (claimed external power supply voltage) is converted and adjusted into the third power supply voltage by the internal driver circuit 200 “when the load current of the display panel is so large that the voltage of the digital power supply terminal DVDD is not greater than the reference voltage”, and “the internal driver circuit 200 and the power management circuit 100 may supply power to the digital power supply terminal DVDD simultaneously”, “to ensure that the voltage of the digital power supply terminal DVDD is greater than or equal to the reference voltage”).
Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Yang et al. (US 2017/0069251).
Regarding claim 14, Jiang discloses all the claim limitations as applied above (see claim 11). In addition, Jiang discloses wherein, in a first mode having a high load of the digital circuit unit, the external power supply voltage is adjusted to be greater than or equal to a minimum operating voltage (VDD min) that ensures operation of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0072]; para[0104]; the “second power supply voltage provided by a power supply terminal VDD” (claimed external power supply voltage) is converted and adjusted into the third power supply voltage by the internal driver circuit 200 “when the load current of the display panel is so large that the voltage of the digital power supply terminal DVDD is not greater than the reference voltage”, and “the internal driver circuit 200 and the power management circuit 100 may supply power to the digital power supply terminal DVDD simultaneously”, “to ensure that the voltage of the digital power supply terminal DVDD is greater than or equal to the reference voltage”), and a second mode having a lower load of the digital circuit unit than the first mode (para[0071]-para[0074]; para[0099]-para[0101]; para[0104]; “When the color of the picture displayed by the display panel is relatively single” or white, “the load current of the display panel is small”, and is smaller than “when the color of a picture displayed by the display panel is complicated”, during which “the load current of the display panel is so large”).
However, Jiang does not appear to expressly disclose wherein, in the second mode having lower load of the digital circuit unit than the first mode, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit.
Yang discloses in a lower load mode, an external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit (para[0106]-para[0107]; para[0128]; para[0131]; e.g., by calculating and using “analog power supply voltage of the source driver chip according to the brightness value required actually” for maximum brightness per sub-pixel (claimed lower load mode), “lower than the voltage corresponding to the maximum brightness”, “the power consumption of the source driver chip may be reduced and… the service life of the source driver chip is thereby prolonged”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s invention, with the teachings in Yang’s invention, to have in the second mode having lower load of the digital circuit unit than the first mode, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit, for the advantage of prolonging the service life of the circuit unit by reducing its power consumption (para[0047]).
Regarding claim 20, Jiang discloses all the claim limitations as applied above (see claim 18). However, Jiang does not appear to expressly disclose when a load current of the digital circuit unit decreases, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit.
Yang discloses when a load current of a digital circuit unit decreases, an external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit (para[0106]-para[0107]; para[0128]; para[0131]; e.g., by calculating and using “analog power supply voltage of the source driver chip according to the brightness value required actually” for maximum brightness per sub-pixel (claimed decreased load current), “lower than the voltage corresponding to the maximum brightness”, “the power consumption of the source driver chip may be reduced and… the service life of the source driver chip is thereby prolonged”; “current flowing… in the actual operation procedure of the source driver chip is reduced accordingly”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s invention, with the teachings in Yang’s invention, to have when a load current of the digital circuit unit decreases, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit, for the advantage of prolonging the service life of the circuit unit by reducing its power consumption (para[0047]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2021/0241685), in view of Chen (US 10,741,147) and Lee et al. (US 2016/0155374), hereinafter Lee ‘374, as applied to claim 15 above, and further in view of Yang et al. (US 2017/0069251).
Regarding claim 17, Jiang, Chen and Lee ‘374 disclose all the claim limitations as applied above (see claim 15). However, Jiang, Chen and Lee ‘374 do not appear to expressly disclose when a load current of the digital circuit unit decreases, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit.
Yang discloses when a load current of a digital circuit unit decreases, an external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit (para[0106]-para[0107]; para[0128]; para[0131]; e.g., by calculating and using “analog power supply voltage of the source driver chip according to the brightness value required actually” for maximum brightness per sub-pixel (claimed decreased load current), “lower than the voltage corresponding to the maximum brightness”, “the power consumption of the source driver chip may be reduced and… the service life of the source driver chip is thereby prolonged”; “current flowing… in the actual operation procedure of the source driver chip is reduced accordingly”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to combine the teachings in Jiang’s, Chen’s and Lee ‘374’s combination, with the teachings in Yang’s invention, to have when a load current of the digital circuit unit decreases, the external power supply voltage is adjusted to not exceed a maximum operating voltage (VDD max) that ensures lifetime of the digital circuit unit, for the advantage of prolonging the service life of the circuit unit by reducing its power consumption (para[0047]).
Response to Arguments
Applicant's arguments filed on 2/23/2026 have been fully considered but they are not persuasive.
Regarding claims 1, 11, 15 and 18, the applicant argues on pages 8-9 of the remarks that “The claimed structure requires both (a) an internal supply being present during driving, and (b) an external supply whose level is separately adjusted by load mode, which is not disclosed or suggested by Jiang”. The examiner respectfully disagrees. As shown in the above rejection which has been modified in the same fashion as the amended claims, Jiang discloses a digital circuit unit supplied with an internal power supply voltage during driving of a display panel (para[0052]; para[0054]; para[0067]; para[0071]-para[0075]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is supplied with “a first power supply voltage” (taken as the claimed internal power supply voltage) at the digital power supply terminal DVDD by power management circuit 100, to drive display panel 10 to display colored or white pictures; “the power supply from the drive device provided in the embodiments… refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”), further supplied with an external power supply voltage that is adjusted according to a load mode of the digital circuit unit (para[0053]-para[0054]; para[0066]-para[0067]; para[0071]-para[0075]; para[0085]; para[0091]; para[0099]-para[0100]; para[0106]-para[0107]; para[0134]; see Figs. 2 and 9, and Table 1; see the digital circuit 201 is further supplied with “a second power supply voltage provided by a power supply terminal VDD” (taken as the claimed external power supply voltage), converted and adjusted into a third power supply voltage by internal driver circuit 200 according to load mode/current at the digital power supply terminal DVDD; the power management circuit 100 supplies voltage to the digital circuit 201 at the digital power supply terminal DVDD jointly with the internal driver circuit 200 in an hybrid way when “the load current is large when the display panel displays the color picture, and the voltage of the digital power supply terminal DVDD is lower than the reference voltage”, to display e.g. colored pictures; “the power supply from the drive device provided in the embodiments of the present disclosure refers to that the power management circuit 100 continuously supplies power to the digital power supply terminal DVDD”, and the external power supply voltage at power supply terminal VDD is provided through the internal driver circuit 200 “to the digital power supply terminal DVDD when the voltage of the digital power supply terminal DVDD is lower than the reference voltage” during a high load mode/current and is stopped “when the voltage of the digital power supply terminal DVDD is not lower than the reference voltage” during a low load mode/current).
Conclusion
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/GLORYVID FIGUEROA-GIBSON/Patent Examiner, Art Unit 2623
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628