DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species IA (including claims 1-2 and 4-15) in the reply filed on 7/15/2026 is acknowledged. The traversal is on the ground(s) that:
examination of all groups represent no serious burden to the Examiner, and
the Applicant should not be required to incur additional costs.
This is not found persuasive because the Applicant has neither provided sufficient evidence that examination of all groups represent no serious burden, nor provided a statement that the identified, distinct groups are obvious alternatives. Absent such evidence, or statement, the Applicant’s arguments are mere conclusory statements, and as such are not persuasive. As noted in the restriction requirement, the product as claimed can be manufactured with a process and/or method distinct from the method as claimed. Therefore, the method requires an additional search for the particular limitations specific to the claimed method. Such additional method-specific searches, including but not limited to different search strategies, different search queries, and different CPC classes/subclasses, represents a serious search burden.
Furthermore, the Applicant is reminded that the non-elected claims may be cancelled and replaced with additional claims directed to the elected invention, without incurring additional cost.
Since the Applicant’s arguments are not persuasive, the requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 4 is objected to because of the following informalities: The Examiner suggests the following amendment to correct an apparent typographic error:
4. The memory device of claim 2, wherein the shared second source/drain region of each pair of the serially connected transistors is an undoped semiconductor material, an intrinsic semiconductor material, [[a]] an n-type doped semiconductor material, or a p-type doped semiconductor material.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4-7 and 11-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 14 and 16-18 of U.S. Patent No. US 12,457,734 B2. Although the claims at issue are not identical, they are not patentably distinct from each other for the following reasons.
Instant application
Reference patent
Difference
Claim 1
A memory device, comprising:
an array of vertically stacked two transistor (2T) memory cells, the array of vertically stacked 2T memory cells, comprising:
pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions;
horizontally oriented access lines separated from the channel regions by a gate dielectric material; and
vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.
Claim 14
A memory device, comprising:
an array of vertically stacked two transistor (2T) memory cells on a substrate, the array of vertically stacked 2T memory cells, comprising:
serially connected horizontally oriented transistors each having an independent first source/drain region and a shared second source/drain region separated by channel regions, and gates opposing the channel regions and separated therefrom by a gate dielectric;
pairs of vertically oriented access lines separated from the channel region by the gate dielectric, wherein:
the pairs of vertically oriented access lines are orthogonal to the substrate;
a first pair of vertically oriented access lines is located between a horizontally oriented digit line and a second pair of vertically oriented access lines,
wherein the horizontally oriented digit line is parallel to the substrate;
Instant application and reference patent both recite 2T memory cells, such that both implicitly require transistor pairs.
Instant application requires serially connected transistors, but does not require horizontal orientation.
Instant application does not explicitly require gates.
Instant application does not require vertically oriented access lines.
Instant application requires vertical digit lines instead of horizontal digit lines.
Claim 4
The memory device of claim 2, wherein the shared second source/drain region of each pair of the serially connected transistors is an undoped semiconductor material, an intrinsic semiconductor material, a an n-type doped semiconductor material, or a p-type doped semiconductor material.
Claim 16
The memory device of claim 14, wherein the shared second source/drain region of the serially connected horizontally oriented transistors is an undoped semiconductor material, an n-type doped semiconductor material, or a p-type doped semiconductor material.
Substantially equivalent
Claim 5
The memory device of claim 4, wherein the channel regions have a different type of doping than the shared second source/drain region of each pair of the serially connected transistors
Claim 17
The memory device of claim 16, wherein the channel regions have a different type of doping than the shared second source/drain region of the serially connected horizontally oriented transistors.
Substantially equivalent
Claim 6
The memory device of claim 4, wherein the channel regions have a different concentration of doping than the shared second source/drain region of each pair of the serially connected transistors.
Claim 18
The memory device of claim 16, wherein the channel regions have a different concentration of doping than the shared second source/drain region of the serially connected horizontally oriented transistors
Substantially equivalent
Claim 7
A memory cell, comprising:
a first horizontally oriented transistor comprising a first source/drain region, a first channel region and a shared source/drain region;
a second horizontally oriented transistor comprising a second source/drain region, a second channel region and the shared source/drain region, wherein the first and second transistors are in a same tier of a vertical stack;
a first horizontally oriented access line separated from the first channel region by a first gate dielectric material;
a second horizontally oriented access line separated from the second channel region by a second gate dielectric material;
a vertically oriented digit line electrically coupled to the first source/drain region of the first horizontally oriented transistor; and
a vertically oriented source line electrically coupled to the second source/drain regions of the second horizontally oriented transistor.
Claim 14
A memory device, comprising:
an array of vertically stacked two transistor (2T) memory cells on a substrate, the array of vertically stacked 2T memory cells, comprising:
serially connected horizontally oriented transistors each having an independent first source/drain region and a shared second source/drain region separated by channel regions, and gates opposing the channel regions and separated therefrom by a gate dielectric;
pairs of vertically oriented access lines separated from the channel region by the gate dielectric, wherein:
the pairs of vertically oriented access lines are orthogonal to the substrate;
first pair of vertically oriented access lines is located between a horizontally oriented digit line and a second pair of vertically oriented access lines,… an independent source/drain region of a first transistor of a memory cell is coupled to a respective horizontally oriented digit line and
an independent source/drain region of a second transistor of the memory cell is coupled to a respective common source line;
Claim 7 of the application is substantially equivalent to the memory cell of claim 1 of the application plus the source line of claim 2 of the application.
The first and second transistors of the application are equivalent to the plurality of transistors of the patent.
First and second access lines of the application are analogous to the pairs of access lines of the patent, with the additional feature of horizontal orientation
Digit lines of application are oriented vertically rather than horizontally
Source line of application is analogous to common source line of patent.
Claim 11
The memory cell of claim 7, wherein the shared second source/drain region is an undoped semiconductor material, a n-type doped semiconductor material, or a p-type doped semiconductor material.
Claim 16
The memory device of claim 14, wherein the shared second source/drain region of the serially connected horizontally oriented transistors is an undoped semiconductor material, an n-type doped semiconductor material, or a p-type doped semiconductor material.
Substantially equivalent
Claim 12
The memory cell of claim 11, wherein the first channel region and the second channel region each have a different type of doping than the shared source/drain region.
Claim 17
The memory device of claim 16, wherein the channel regions have a different type of doping than the shared second source/drain region of the serially connected horizontally oriented transistors.
Substantially equivalent
Claim 13
The memory cell of claim 11, wherein the first channel region and the second channel region each have a different concentration of doping than the shared source/drain region.
Claim 18
The memory device of claim 16, wherein the channel regions have a different concentration of doping than the shared second source/drain region of the serially connected horizontally oriented transistors.
Substantially equivalent
As noted above, the claims of the application are distinguished over the claims of the reference patent by the orientation of the array. A person of ordinary skill in the art of semiconductor manufacturing would recognize that the orientation of a memory array is a matter of obvious design choice. Therefore, memory array orientation is insufficient to patentably distinguish the claims of the application from the corresponding claims of the reference patent.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 and 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites memory cells comprising pairs of serially connected transistors, each pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by channel regions. Therefore, each pair of transistors requires a plurality of channels arranged between a single independent source/drain region and a single shared source/drain region.
The application as originally filed provides support for an array of stacked memory cells 110, including pairs of serially-connected transistors 115-A/115-B, independent source/drain regions 221 and 224, shared source/drain region 223, and channels 225 and 227 (figs. 1A-1B & 2, and associated text). This arrangement does not provide support for a plurality of channels between an independent source/drain and a shared source/drain. Rather, first channel 225 is arranged between first independent source/drain 221 and shared source/drain 223, and second channel 227 is arranged between second independent source/drain 224 and shared source/drain 223.
This renders the scope of claim 1 indefinite, as it is unclear if the claimed channels as claimed both are arranged between the same two source/drain regions, or arranged between respective source/drain regions as disclosed in the written specification.
For the purposes of compact prosecution, the Examiner has interpreted claim 1 to mean:
1. A memory device, comprising:
an array of vertically stacked two transistor (2T) memory cells, the array of vertically stacked 2T memory cells, comprising:
pairs of serially connected transistors, each transistor of the pair of serially connected transistors having an independent first source/drain region and a shared second source/drain region separated by respective channel regions;
horizontally oriented access lines separated from the channel regions by a gate dielectric material; and
vertically oriented digit lines electrically coupled to the first source/drain regions of the serially connected transistors.
Claims 2 and 4-6 are rejected under 35 USC § 112(b) for implicitly including the indefinite subject matter above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-9, 11-13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (PG Pub. No. US 2020/0402588 A1).
Regarding claim 1, Lee teaches a memory device (¶ 0030 & fig. 2: 200), comprising:
an array of vertically stacked two transistor (2T) memory cells (fig. 2: 2T cells 201 and/or 212 stacked in rows 281 and 282), the array of vertically stacked 2T memory cells, comprising:
pairs of serially connected transistors (¶ 0033: 202, 203), each transistor of the pair of serially connected transistors having an independent first source/drain region (¶ 0033: 206, 209) and a shared second source/drain region (¶ 0033 & fig. 2: source 205 and drain 210 electrically connected together) separated by respective channel regions (¶ 0033: channel portions of wells 207 and 211);
horizontally oriented access lines (¶ 0032: 231, 232) separated from the channel regions by a gate dielectric material (implicit: 202 and 203 are MOSFET devices, and therefore include non-illustrated gate dielectric between gate 204/208 and well 207/211); and
vertically oriented digit lines (¶ 0032: 238) electrically coupled to the first source/drain regions of the serially connected transistors (fig. 2: 238 electrically coupled to s/d regions 206).
Regarding claim 2, Lee teaches the memory device of claim 1, comprising a source line (¶ 0031: 240) electrically coupled to an independent third source/drain region (¶ 0033: 209) of each pair of the serially connected transistors (fig. 2: 240 electrically connected to 209 of each transistor pair).
Regarding claim 4, Lee teaches the memory device of claim 2, wherein the shared second source/drain region of each pair of the serially connected transistors is an undoped semiconductor material, an intrinsic semiconductor material, [[a]] an n-type doped semiconductor material, or a p-type doped semiconductor material (¶¶ 0046, 0052: at least portion 210 includes halo and/or LDD implant dopant, and/or an n-type region).
Regarding claim 5, Lee teaches the memory device of claim 4, wherein the channel regions have a different type of doping than the shared second source/drain region of each pair of the serially connected transistors (¶ 0046 & figs. 2, 5: 202 and 203 are MOSFET devices, and therefore have different channel/well doping from s/d doping).
Regarding claim 6, Lee teaches the memory device of claim 4, wherein the channel regions have a different concentration of doping than the shared second source/drain region of each pair of the serially connected transistors (¶ 0046 & figs. 2, 5: 202 and 203 are MOSFET devices, and source/drain regions include pocket/halo implants and/or LDD implants; therefore the channels have different net doping from the net source/drain region doping).
Regarding claim 7, Lee teaches a memory cell (¶ 0030 & fig. 2: 200), comprising:
a first horizontally oriented transistor (¶ 0031: 202) comprising a first source/drain region (¶ 0033: 206), a first channel region (¶ 0033: channel portion of well 207) and a shared source/drain region (¶ 0033 & fig. 2: source 205 and drain 210 electrically connected together);
a second horizontally oriented transistor (¶ 0031: 203) comprising a second source/drain region (¶ 0033: 209), a second channel region (211) and the shared source/drain region (¶ 0033 & fig. 2: 205/210 electrically connected to 203), wherein the first and second transistors are in a same tier of a vertical stack (fig. 2: 202 and 203 arranged in same vertical tier);
a first horizontally oriented access line (¶ 0032: WLS/231) separated from the first channel region by a first gate dielectric material (implicit: 202=MOSFET w/ gate 204 connected to WLS/231);
a second horizontally oriented access line (WL/232) separated from the second channel region by a second gate dielectric material (figs. 2 & 5: 203 configured as MOSFET with gate 208 connected to WL/232, such that a non-illustrated gate dielectric is implicitly arranged between WL/232 and 211);
a vertically oriented digit line (¶ 0032: BL/238) electrically coupled to the first source/drain region of the first horizontally oriented transistor (fig. 2: 238 electrically coupled to 206); and
a vertically oriented source line (¶ 0031: CSL/240) electrically coupled to the second source/drain regions of the second horizontally oriented transistor (fig. 2: CSL/240 electrically coupled to 209).
Regarding claim 8, Lee teaches the memory cell of claim 7, wherein a dimension of the first horizontally oriented access line relative to the first horizontally oriented transistor is different than a dimension of the second horizontally oriented access line relative to the second horizontally oriented transistor (fig. 2: 231 higher than 232, such that connection between 231 and 204 is l0nger than connection between 232 and 208).
Regarding claim 9, Lee teaches the memory cell of claim 8, wherein the dimension of the first horizontally oriented access line relative to the first horizontally oriented transistor is greater than the dimension of the second horizontally oriented access line relative to the second horizontally oriented transistor (fig. 2: distance from 231 to 207 greater than distance from 232 to 211).
Regarding claim 11, Lee teaches the memory cell of claim 7, wherein the shared second source/drain region is an undoped semiconductor material, a n-type doped semiconductor material, or a p-type doped semiconductor material (¶¶ 0046, 0052: at least portion 210 includes halo and/or LDD implant dopant, and/or an n-type region).
Regarding claim 12, Lee teaches the memory cell of claim 11, wherein the first channel region and the second channel region each have a different type of doping than the shared source/drain region (¶ 0046 & figs. 2, 5: 202 and 203 are MOSFET devices, and therefore have different channel/well doping from s/d doping).
Regarding claim 13, Lee teaches the memory cell of claim 11, wherein the first channel region and the second channel region each have a different concentration of doping than the shared source/drain region (¶ 0046 & figs. 2, 5: 202 and 203 are MOSFET devices, and source/drain regions include pocket/halo implants and/or LDD implants; therefore the channels have different net doping from the net source/drain region doping).
Regarding claim 15, Lee teaches the memory cell of claim 7, wherein one of the first horizontally oriented transistor and the second horizontally oriented transistor comprises an access transistor and another of the first horizontally oriented transistor and the second horizontally oriented transistor comprises storage transistor (¶ 0033: 202 is a memory transistor, 203 is a pass transistor).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 10, Lee teaches the memory cell of claim 8, wherein the dimension of the first horizontally oriented access line relative to the first horizontally oriented transistor is different than the dimension of the second horizontally oriented access line relative to the second horizontally oriented transistor (fig. 2: distance between 231 and 202 is different than distance between 232 and 203).
Lee does not explicitly teach the dimension of the first horizontally oriented access line relative to the first horizontally oriented transistor is less than the dimension of the second horizontally oriented access line relative to the second horizontally oriented transistor.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to reduce the distance between the first horizontally oriented access line relative to the first horizontally oriented transistor, and/or increase the dimension of the second horizontally oriented access line relative to the second horizontally oriented transistor, as a means to optimize properties such as parasitic resistance, circuit timing, and circuit layout.
Furthermore, such a modification would have involved a mere change in the size of a component (distance between an access line and a transistor). Absent persuasive evidence that the particular dimension is critical to the claimed invention, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 7 above, and further in view of Han et al. (PG Pub. No. US 2018/0122943 A1).
Regarding claim 14, Lee teaches the memory cell of claim 7, including first and second gate dielectric material (202 and 203 are MOSFET devices, and therefore implicitly include gate dielectric material between gates 204 and 208, and respective channel regions).
Lee does not teach wherein the first gate dielectric material and the second gate dielectric material are gate all around structures.
Han teaches a memory cell (¶ 0233: 850F) including shared source/drain regions (fig. 62: source/drain region 16 shared by adjacent transistors), and further teaches memory cells including gate dielectric material (¶ 0231: 162) configured as gate all around structures (figs. 70A-70B, 71A-71B: gate 160 and unlabeled gate dielectric fully surround channel region 124).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the gate dielectric of Lee with a gate-all-around structure, as a means to optimize the electric field, enhancing control of carriers in the channel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
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/BRIAN TURNER/Examiner, Art Unit 2818
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