DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, 11-15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Terai (U.S. Patent No. 10,522,595) in view of Maejima et al. (U.S. Patent No. 8,717,801).
Regarding to claim 1, Terai teaches a semiconductor device comprising:
a plurality of first conductive lines extending in a first direction (Figs. 2-3, elements 120; column 9, lines 38-40);
a plurality of second conductive lines disposed separately from and over the plurality of first conductive lines and extending in a second direction intersecting the first direction (Figs. 2-3, elements 130; column 9, lines 45-46); and
a plurality of memory cells respectively overlapping intersection areas between the plurality of first conductive lines and the plurality of second conductive lines (Figs. 2-3, elements 150; column 12, lines 34-35),
wherein the plurality of memory cells includes a plurality of first memory cells (Fig. 2, columns at positions 1-1, 1-3, 2-2, 2-4, 3-1, 3-3, 4-2, 4-4) each including a first memory pattern (Figs. 2-3, elements 152; column 12, lines 41-42) and a first selector pattern disposed on the first memory pattern (Figs. 2-3, elements SW2; column 12, lines 41-42), and a plurality of second memory cells (Fig. 2, columns at positions 1-2, 1-4, 2-1, 2-3, 3-2, 3-4, 4-1, 4-3) each including a second selector pattern and a second memory pattern disposed on the second selector pattern (Figs. 2-3, elements SW2; column 12, lines 41-42), each of the first memory pattern and the second memory pattern (Figs. 2-3, elements 152; column 12, lines 41-42) configured to store data and each of the first selector pattern and the second selector pattern configured to exhibit electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage (Fig. 6), and
wherein one of the plurality of first memory cells and one of the plurality of second memory cells are alternately arranged in each of the first direction and the second direction (Figs. 2-3).
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Terai does not disclose the electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage exhibit by the first memory pattern and the second memory pattern are different.
Maejima discloses electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage exhibit by selected and non-selected memory cells are different (Figs. 4A-B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Terai in view of Maejima to configure different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage by assigning first and second memory patterns as selected and non-selected cells in order to increase stability.
Regarding to claim 2, Terai teaches the plurality of first memory cells are arranged in a row in a third direction intersecting the first direction and the second direction (Fig. 2, please also see the attached figures).
Regarding to claim 3, Terai teaches a distance between centers of two first memory cells that are adjacent in the first direction or the second direction is larger than a distance between centers of two first memory cells that are adjacent in the third direction (Fig. 2).
Regarding to claim 4, Terai teaches the plurality of second memory cells are arranged in a row in a third direction intersecting the first direction and the second direction (Fig. 2).
Regarding to claim 5, Terai teaches a distance between centers of two second memory cells that are adjacent in the first direction or the second direction is larger than a distance between centers of two second memory cells that are adjacent in the third direction (Fig. 2).
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Regarding to claim 6, Terai teaches the first memory pattern and the second selector pattern are located at a first level in a vertical direction, and the second memory pattern and the first selector pattern are located at a second level in the vertical direction (Figs. 2-3).
Regarding to claim 8, Terai teaches at least one of the first selector pattern and the second selector pattern includes an insulating material and a dopant doped into the insulating material, and the dopant is configured to generate a trap site for providing a movement path for conductive carriers in the insulating material (Fig. 3, column 11, lines 28-35).
Regarding to claim 11, Terai teaches the first memory pattern and the second memory pattern are identical to each other (Figs. 2-3).
Regarding to claim 12, Terai teaches the first selector pattern and the second selector pattern are identical to each other (Figs. 2-3).
Regarding to claim 13, Terai teaches a first insulating layer filling a space between the first memory pattern and the second selector pattern; a second insulating layer filling a space between the second memory pattern and the first selector pattern, wherein the first insulating layer and the second insulating layer are identical to each other (Figs. 2-3, same insulator 170 filled in the spaces between the first memory pattern and the second selector pattern and between the second memory pattern and the first selector pattern).
Regarding to claim 14, Terai teaches method for fabricating a semiconductor device, comprising:
forming a plurality of first conductive lines extending in a first direction (Figs. 2-3, elements 120; column 9, lines 38-40);
forming, over the plurality of first conductive lines (Figs. 2-3, elements 120; column 9, lines 38-40), a plurality of memory cells including a plurality of first memory cells (Fig. 2, columns at positions 1-1, 1-3, 2-2, 2-4, 3-1, 3-3, 4-2, 4-4) each including a first memory pattern (Figs. 2-3, elements 150; column 12, lines 34-35) and a first selector pattern disposed on the first memory pattern (Figs. 2-3, elements SW2; column 12, lines 41-42) and a plurality of second memory cells (Fig. 2, columns at positions 1-2, 1-4, 2-1, 2-3, 3-2, 3-4, 4-1, 4-3) each including a second selector pattern (Figs. 2-3, elements SW2; column 12, lines 41-42) and a second memory pattern disposed on the second selector pattern (Figs. 2-3, elements 152; column 12, lines 41-42), each of the first memory pattern and the second memory pattern configured to store data and each of the first selector pattern and the second selector pattern configured to exhibit electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage (Fig. 6); and
forming a plurality of second conductive lines over the plurality of memory cells to extend in a second direction intersecting the first direction so that the plurality of memory cells is coupled between the plurality of first conductive lines and the plurality of second conductive lines (Figs. 2-3, elements 130; column 9, lines 45-46); and
a plurality of memory cells respectively overlapping intersection areas between the plurality of first conductive lines and the plurality of second conductive lines (Figs. 2-3, elements 150; column 12, lines 34-35),
wherein one of the plurality of first memory cells and one of the plurality of second memory cells are alternately arranged in each of the first direction and the second direction (Figs. 2-3).
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Terai does not disclose the electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage exhibit by the first memory pattern and the second memory pattern are different.
Maejima discloses electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage exhibit by selected and non-selected memory cells are different (Figs. 4A-B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Terai in view of Maejima to configure different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage by assigning first and second memory patterns as selected and non-selected cells in order to increase stability.
Regarding to claim 15, Terai teaches the forming of the plurality of memory cells comprises: forming the first memory pattern and the second selector pattern on a first conductive line; and forming the first selector pattern and the second memory pattern on the first memory pattern and the second selector pattern, respectively (Fig. 2).
Regarding to claim 18, Terai teaches the forming of the first memory pattern or the forming of the second memory pattern comprises: forming a memory layer; and selectively etching the memory layer (Figs. 16B-C).
Regarding to claim 20, Terai teaches the plurality of first memory cells is arranged in a row in a third direction intersecting the first direction and the second direction, and the plurality of second memory cells is arranged in a row in the third direction (Fig. 2).
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Allowable Subject Matter
Claims 7, 9-10, 16-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 7, the prior art fails to anticipate or render obvious the claimed limitations including “at least one of the first memory pattern and the second memory pattern includes a magnetic tunnel junction structure” in combination with the limitations recited in claim 1.
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the second selector pattern includes the insulating material and a dopant doped into the insulating material” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 9.
Regarding to claim 10, the prior art fails to anticipate or render obvious the claimed limitations including “the first selector pattern includes a same insulating material as the second insulating layer and a dopant doped into the insulating material” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 10.
Regarding to claim 16, the prior art fails to anticipate or render obvious the claimed limitations including “doping a dopant for generating a trap site into a part of the first insulating layer exposed by the first mask pattern, the trap site providing a movement path of conductive carriers in the first insulating layer” in combination with the limitations recited in claims 14-15 and the rest of limitations recited in claim 16.
Regarding to claim 17, the prior art fails to anticipate or render obvious the claimed limitations including “doping a dopant for generating a trap site into a part of the second insulating layer exposed by the second mask pattern, the trap site providing a movement path of conductive carriers in the second insulating layer” in combination with the limitations recited in claims 14-15 and the rest of limitations recited in claim 16.
Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “the memory layer includes a magnetic tunnel junction structure” in combination with the limitations recited in claims 14-15, 18, and the rest of limitations recited in claim 19.
Pertinent Art
For the benefits of the Applicant, US-12232429-B2, US-8482955-B2, US-9530822-B2, US-8711596-B2, US-9013911-B2, US-10283561-B2, and US-11227991-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose “each of the first memory pattern and the second memory pattern configured to store data and each of the first selector pattern and the second selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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