Prosecution Insights
Last updated: July 17, 2026
Application No. 18/645,319

SEMICONDUCTOR STRUCTURE, METHOD FOR FABRICATING THEREOF, AND METHOD FOR FABRICATING SEMICONDUCTOR LAYOUT

Non-Final OA §102§103§112
Filed
Apr 24, 2024
Priority
Aug 11, 2021 — CN 202110919203.0 +2 more
Examiner
MICHAUD, NICHOLAS BRIAN
Art Unit
Tech Center
Assignee
Fujian Jinhua Integrated Circuit Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
42 granted / 57 resolved
+13.7% vs TC avg
Strong +32% interview lift
Without
With
+31.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
21 currently pending
Career history
80
Total Applications
across all art units

Statute-Specific Performance

§103
87.1%
+47.1% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
10.0%
-30.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 57 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application Claims 1-26 remain pending in this application. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Objections Claim 24 is objected to because of the following informalities: the claim recites “one of the end lines of first portion”, in lines 3 and 4, it appears it should read “one of the end lines of the first portion” or another appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7, 9, 21, 23, and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 7, it recites the limitation "the cavity" in line 1. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the at least one cavity”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required. Regarding claim 9, it recites the limitation "a side of one of the merged patterns" and “a side of the other one of the merged patterns” in lines 3 and 4. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a side of one of the two merged patterns” and “a side of the other one of the two merged patterns”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required. Regarding claim 21, it recites the limitation "a side of one of the merged patterns" and “a side of the other one of the merged patterns” in lines 4 and 5. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a side of one of the two merged patterns” and “a side of the other one of the two merged patterns”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required. Regarding claim 23, it recites the limitation "the merged pattern" in line 3. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “the at least one merged pattern”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required. Regarding claim 26, it recites the limitation "a side of one of the merged patterns" and “a side of the other one of the merged patterns” in lines 4 and 5. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a side of one of the two merged patterns” and “a side of the other one of the two merged patterns”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4, 11, 12, 18, 19, 21, 23, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagahara et al (US 20090298205 A1, as cited in IDS dated 06/28/2024, hereafter Nagahara). Regarding claim 1, Nagahara discloses: A semiconductor structure (Nagahara fig 9A, 9B), comprising: a substrate (Nagahara, ¶0006); a plurality of metal patterns (Nagahara 120, 140, ¶0070), disposed on the substrate (Nagahara fig 9A, 9B); and at least one merged pattern (Nagahara A, 120, 140, ¶0070), disposed between adjacent two of the metal patterns (Nagahara fig 9A, 9B, A is disposed between 120 and 140), wherein the at least one merged pattern comprises a first outer line (Nagahara inner 120, fig 9A, 9B, at least outside with regard to a centerline A), a central line (Nagahara A) and a second outer line (Nagahara inner 140, fig 9A, 9B, at least outside with regard to a centerline A) sequentially arranged along a first direction (Nagahara vertical direction with regard to fig 9A, 9B) and connected with each other (Nagahara fig 9A, 9B, 120 and 140 connect at A), and one short axis of the first outer line, one short axis of the central line and one short axis of the second outer line are misaligned along the first direction (Nagahara fig 9A, 9B, a short axis aligned with centerlines of protrusions of 120 and 140, oriented in a horizontal direction with regard to fig 9A, 9B, are misaligned with each other, the central axis of the centerline A is misaligned with regard to the same direction). Regarding claim 4, Nagahara discloses: The semiconductor structure of claim 1, wherein the at least one merged pattern (Nagahara A, 120, 140) comprises at least one cavity located between the first outer line (Nagahara inner 120, fig 9A, 9B) and the second outer line (Nagahara inner 140)(Nagahara fig 9A, a cavity bounded at least between lower right hand corner of small protrusion of 140 and inner edge of larger portion of 120, under a broadest reasonable interpretation of “cavity”). Regarding claim 11, Nagahara discloses: The semiconductor structure of claim 1, wherein the metal patterns (Nagahara 120, 140, ¶0070) comprise a plurality of first metal patterns (Nagahara 120) and a plurality of second metal patterns (Nagahara 140), wherein the first metal patterns and the second metal patterns are disposed on the substrate and alternatively arranged along the first direction (Nagahara fig 9A, 9B). Regarding claim 12, Nagahara discloses: The semiconductor structure of claim 11, wherein, the first outer line (Nagahara inner 120) is disposed near one of the second metal patterns (Nagahara 140)(Nagahara fig 9A, 9B), and the second outer line (Nagahara inner 140) is disposed near one of the first metal patterns (Nagahara 120)(Nagahara fig 9A, 9B), wherein the length of the first outer line is not equal to the length of the second outer line (Nagahara fig 9A, 9B); and the width of the at least one merged pattern (Nagahara A, 120, 140) is larger than the width of each of the first metal patterns and the width of each of the second metal patterns (Nagahara fig 9A, 9B). Regarding claim 18, Nagahara discloses: A semiconductor structure (Nagahara fig 9A, 9B), comprising: a substrate (Nagahara, ¶0006); a plurality of metal patterns (Nagahara 120, 140, ¶0070) on the substrate and arranged along a first direction (Nagahara vertical direction with regard to fig 9A, 9B)(Nagahara fig 9A, 9B); and at least one merged pattern (Nagahara A, 120, 140, ¶0070), disposed between adjacent two of the metal patterns (Nagahara fig 9A, 9B, A is disposed between 120 and 140), wherein the at least one merged pattern comprises two short axes (Nagahara fig 9A, 9B, a short axis aligned with centerlines of protrusions of 120 and 140) disposed opposite each other and arranged along a second direction (Nagahara fig 9A, 9B, horizontally with respect to fig 9A, 9B)(Nagahara fig 9A, 9B, disposed opposite each other along centerline A) perpendicular to the first direction (Nagahara fig 9A, 9B), each of the short axes comprises a recessed region and at least a protruded region (Nagahara fig 9A, at least recessed with respect to corresponding 120/140 and opposite 120/140). Regarding claim 19, Nagahara discloses: The semiconductor structure of claim 18, wherein each of the recessed region and the protruded region comprises a curved surface (Nagahara fig 9A, 9B, under a broadest reasonable interpretation of curved surface). Regarding claim 21, Nagahara discloses: The semiconductor structure of claim 18, wherein the at least one merged pattern (Nagahara A, 120, 140, ¶0070) comprises two merged patterns arranged along the second direction (Nagahara fig 9A, 9B, horizontally with respect to fig 9A, 9B)(Nagahara fig 9A, 9B), and one of the metal patterns extends, along the first direction (Nagahara vertical direction with regard to fig 9A, 9B), from a side of one of the merged patterns (as best understood to mean “a side of one of the two merged patterns”) to a side of the other one of the merged patterns (as best understood to mean “a side of the other one of the two merged patterns”)(Nagahara fig 9A, 9B). Regarding claim 23, Nagahara discloses: A semiconductor structure (Nagahara fig 9A, 9B), comprising: a substrate (Nagahara, ¶0006); a plurality of metal patterns (Nagahara 120, 140, ¶0070), disposed on the substrate (Nagahara fig 9A, 9B); and at least one merged pattern (Nagahara A, 120, 140, ¶0070), disposed between adjacent two of the metal patterns (Nagahara fig 9A, 9B, A is disposed between 120 and 140), wherein the merged pattern (as best understood to mean “the at least one merged pattern”) comprises a first portion (Nagahara inner 120) and a second portion (Nagahara inner 140) sequentially arranged along a first direction (Nagahara vertical direction with regard to fig 9A, 9B) and connected with each other (Nagahara fig 9A, 9B, 120 and 140 connect at A), the first portion and the second portion each comprises two ends opposite each other (Nagahara fig 9A, 9B) and arranged along a second direction (Nagahara fig 9A, 9B, horizontally with respect to fig 9A, 9B) which is perpendicular to the first direction (Nagahara fig 9A, 9B), one end of the first portion extends beyond one end of the second portion to form a first offset (Nagahara fig 9A, 9B, 120 extends up beyond protrusion of 140), the other end of the second portion extends beyond the other end of the first portion to form a second offset (Nagahara fig 9A, 9B, 140 extends down beyond protrusion of 120). Regarding claim 24, Nagahara discloses: The semiconductor structure of claim 23, wherein the first portion (Nagahara inner 120) and the second portion (Nagahara inner 140) comprise end lines (Nagahara fig 9A, 9B, each 120 and 140 have horizontal protrusions, at least at the merge end), respectively, and, as viewed along the first direction, one of the end lines of first portion overlaps the second portion, and one of the end lines of second portion overlaps the first portion (Nagahara fig 9A, 9B, at least overlapping along centerline A). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nagahara et al (US 20090298205 A1, as cited in IDS dated 06/28/2024, hereafter Nagahara), as applied to claim 1 above, and further in view of Chang et al (US 20200118812 A1, hereafter Chang). Regarding claim 3, Nagahara teaches: The semiconductor structure of claim 1; the metal patterns are conductive line patterns (Nagahara ¶0096, “wiring patterns”, therefore must at least be capable of being conductive). Nagahara does not teach: wherein the semiconductor structure is a partial structure of a semiconductor memory device, wherein the substrate comprises a plurality of active areas; and each of the conductive line patterns is electrically connected to each of the active areas respectively. Chang, in the same field of endeavor of semiconductor device manufacturing, teaches: a semiconductor structure is a partial structure of a semiconductor memory device (Chang 200, ¶0037, fig 12, 13), wherein a substrate (Chang 220) comprises a plurality of active areas (Chang 222/412/414, ¶0037, 0040, fig 12, 16); and conductive line patterns (Chang 230, under a broadest reasonable interpretation) is electrically connected to each of the active areas respectively (Chang ¶0037, fig 12). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the semiconductor structure of Nagahara such that “the semiconductor structure is a partial structure of a semiconductor memory device, wherein the substrate comprises a plurality of active areas; and each of the conductive line patterns is electrically connected to each of the active areas respectively”, as taught by Chang, in order to reliably connect the conductive line to active area of memory cells, thereby avoiding open-circuit failures due to overlay error (Nagahara ¶0005, 0083), and/or in order to realize the interconnect benefit of Nagahara in a semiconductor memory device. Allowable Subject Matter Claims 2, 5, 6, 8, 10, 13-17, 20, 22, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 7, 9, and 26 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 272-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS B. MICHAUD/ EXAMINER Art Unit 2818 /Mounir S Amer/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Apr 24, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+31.6%)
3y 3m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 57 resolved cases by this examiner. Grant probability derived from career allowance rate.

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