CTNF 18/645,374 CTNF 99851 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Claims 1-21 are pending. Claim Objections 07-29-01 AIA Claim s 8 and 18 are objected to because of the following informalities: Claim 8 is objected to for clarity . Currently, claim 8 reads “wherein a height from the package substrate to an uppermost portion of the first stack structure is higher than a height from the package substrate to an uppermost portion of the second stack structure.” Examiner recommends that this claim language is changed to read “wherein a distance from the package substrate to an uppermost portion of the first stack structure is greater than a distance from the package substrate to an uppermost portion of the second stack structure,” or similar, to clarify the claim language. Claim 18 is objected to for clarity . Currently, claim 18 reads “wherein a support is inserted into at least one of the first stack structure and the second stack structure to face the first concave portion and the second protrusion to each other and the first protrusion and the second concave portion to each other.” Examiner recommends that changes are made to this claim in order to remove the method step of “inserted” from the product claim, and additionally to clarify the structural limitation in regards to the phrase “to face.” Claim 21 is objected to for clarity . Currently, claim 21, line 5 reads “wherein a concave portion of one of the first stack structures is positioned adjacent to a concave portion of the second stack structure.” Claim 21 line 5 should instead read “wherein a concave portion of one of the first stack structures is positioned adjacent to a concave portion of one of the second stack structures.” Appropriate correction is required. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. 06-11-01 AIA The following title is suggested: STACK CHIP PACKAGE HAVING UNEVEN SIDEWALLS INCLUDING ALTERNATING PROTRUDING AND CONCAVE PORTIONS Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 4, 5, 16, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 4, the claim fails to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, it is unclear whether the “thickness of the first concave portion and the first protrusion is a sum of a thickness” of all of the semiconductor chips in the first stack and the insulating adhesive layers combined or if this value refers to the sum of a thickness of an individual semiconductor chip and its respective insulating adhesive layer. For the purposes of examination, the latter interpretation will be used, wherein the sum is of a thickness of an individual semiconductor chip and its respective insulating adhesive layer, as supported by at least Figure 1. The examiner recommends that amendment be made to the claim to clarify what value the “sum” refers to. Regarding claim 5, the term “relatively thin” is a relative term which renders the claim indefinite. The term “relatively thin” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, it is unclear as to the meaning of the thickness of “a semiconductor chip” as it is not placed in reference to any other reference point. For the purposes of examination, it will be interpreted that a single semiconductor chip in either the first stack structure or the second stack structure is thinner than any other chip in either stack, as supported by at least Figure 6. Accordingly, it will be interpreted that the insulating adhesive layer attached to the semiconductor chip having the “relatively thin” thickness has a thickness thicker than a thickness of the adhesive layer attached to any of the other semiconductor chips in either stack. Regarding claim 16, the claim fails to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, it is unclear how the claim limitation “wherein numbers of the semiconductor chips in the first stack structure are substantially equal to or different from numbers of the semiconductor chips in the second stack structure” limits the invention. The number of semiconductor chips in the first stack structure can only be equal to or different from the number of the semiconductor chips in the second stack structure. For the purposes of examination, it will be interpreted that the number of the semiconductor chips in the first stack structure is equal to or different from the number of the semiconductor chips in the second stack structure. Regarding claim 21, the claim fails to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, it is unclear how the claim limitation “wherein a concave portion of one of the first stack structures is positioned adjacent to a concave portion of the second stack structure and vice versa” limits the claim. If the concave portion of one of the first stack structures is adjacent to the concave portion of the second stack structure, the concave portion of the second stack structure must necessarily be adjacent to the concave portion of the first stack structure, rendering “and vice versa” moot. For the purposes of examination, it will be interpreted that the applicant intends that “wherein a concave portion of one of the first stack structures is positioned adjacent to a protrusion of the second stack structure, and wherein a protrusion of the first stack structure is positioned adjacent to a concave portion of the second stack structure,” as supported by at least Figures 1 and 3-13. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim 21 is rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Park et al. (US PGPub 2015/0200187; herein known as Park) Regarding claim 21, Park teaches (annotated Fig. 1D below) a stack chip package comprising: first (100, [0087]) and second (200, [0087]) stack structures positioned adjacent to each other, wherein each of the first and second stack structures has uneven sidewalls (see figure) including alternating protruding and concave portions (P1, C1, P2, C2), and wherein a concave portion (C1) of one of the first stack structures (100, [0087]) is positioned adjacent to a concave (P2) portion of the second stack structure (200) and vice versa (P1, C2) thus reducing the overall footprint area of the stack chip package ([0168]) . PNG media_image1.png 380 411 media_image1.png Greyscale Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 6, 8-11, 13, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park et al. (US PGPub 2022/0077114; herein known as Park2) . Regarding claim 1, Park teaches (annotated Fig. 1D below) a stack chip package comprising: a first stack structure (100, [0087]) including a plurality of semiconductor chips (101, [0087]) stacked on a package substrate (300, [0087]), the first stack structure including a first sidewall portion (S1) and a second sidewall portion (S2), wherein the plurality of the semiconductor chips in the first stack structure are stacked to alternately form a first concave portion (C1) and a first protrusion (P1) at the first sidewall portion; a second stack structure (200, [0087]) including a plurality of semiconductor chips (201, [0087]) stacked on the package substrate, the second stack structure including a third sidewall portion (S3) facing the first sidewall portion and a fourth sidewall portion (S4), wherein the plurality of the semiconductor chips in the second stack structure are stacked to alternately form a second concave portion (C2) and a second protrusion (P2) at the third sidewall portion; wherein the first concave portion (C1) of the first stack structure (100) faces the second protrusion (P2) of the second stack structure (200) and the first protrusion (P1) of the first stack structure faces the second concave portion (C2) of the second stack structure. PNG media_image2.png 380 411 media_image2.png Greyscale Park does not explicitly teach a passive element integrated on the package substrate outside the second sidewall portion of the first stack structure and/or the fourth sidewall portion of the second stack structure. Park2 teaches (Fig. 1) a passive element (610, [0025]) integrated on the package substrate (200, [0022]) outside the second sidewall portion (outer wall) of the first stack structure (300, [0022]). Because Park and Park2 are both directed toward stack chip packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park and of Park2 to include a passive element integrated on the package substrate outside the second sidewall portion of the first stack structure in order to provide improvement of electrical characteristics and reliability of signal characteristics of the stack package (Park2, [0025]). Regarding claim 2, Park in view of Park2 teaches the stack chip package of claim 1, wherein a thickness of the first concave portion corresponds to a thickness of the second protrusion and a thickness of the first protrusion corresponds to a thickness of the second concave portion. Park teaches wherein the first and second stack structures can have the same structure ([0087]), thus the thickness of the first concave portion and of the second protrusion, and the thickness of the first protrusion and of the second concave portion must necessarily correspond. Examiner notes, that for the purpose of examination, it has been interpreted that the first concave portion and the second protrusion each have a thickness, and the first protrusion and second concave portion each have a thickness. The limitation “correspond” is not interpreted to place further limitation on the claim, absent any further detail of the meaning of the term in the specification. Regarding claim 3, Park in view of Park2 teaches the stack chip package of claim 1, further comprising an insulating adhesive layer (103, 203, [0088]) configured to attach the plurality of the semiconductor chips (101, [0088]) of the first stack structure (100, [0088]) to each other and the plurality of the semiconductor chips (201, [0088]) of the second stack structure (200, [0088]) to each other. Regarding claim 4, Park in view of Park2 teaches the stack chip package of claim 3, wherein a thickness of the first concave portion and the first protrusion is a sum of a thickness of each of the semiconductor chips in the first stack structure and a thickness of the insulating adhesive layer attached to the semiconductor chips of the first stack structure, and wherein a thickness of the second concave portion and the second protrusion is a sum of a thickness of each of the semiconductor chips in the second stack structure and a thickness of the insulating adhesive layer attached to the semiconductor chips of the second stack structure. The concave portions and protrusions include both the semiconductor chips in addition to the adhesive layer, and thus, the thickness of the concave portion and of the protrusion can be determined to be the sum of the thickness of the corresponding chip and its respective adhesive layer. Regarding claim 6, Park in view of Park2 teaches the stack chip package of claim 1, but does not explicitly teach further comprising a control chip arranged between the first stack structure and the package substrate. Park2 teaches (Fig. 1) further comprising a control chip (710, [0063]) arranged between the first stack structure (300, [0063]) and the package substrate (200, [0063]). Because Park and Park2 are both directed toward stack chip packaging, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Park and Park2 to include further comprising a control chip arranged between the first stack structure and the package substrate in order to provide support to the chip stack, and provide reliable direct bonding from the chip stack to the controlling system (Park2, [0063]). Regarding claim 7, Park in view of Park2 teaches (Park2, Fig. 1) the stack chip package of claim 6, wherein the control chip has a size smaller than a size of the semiconductor chips in the first stack structure (710 has a shorter width than 301) and a support (730, [0063]) is arranged in the space between the first stack structure and the package substrate ([0063]) but does not explicitly teach wherein the control chip is positioned adjacent to the first sidewall portion of the first stack structure to form a space between the first stack structure and the package substrate. The specification of the instant application is silent to criticality of the positioning of the control chip "adjacent to the first sidewall portion of the first stack structure," and therefore fails to teach criticality of the claimed feature. Park2 teaches a stack chip package having a control chip underneath the first stack structure, in addition to a support arranged in the space between the first stack structure and the package substrate, therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the support of Park2 could be arranged in any position under the chip with the predictable result of stabilizing the chip stack. See MPEP 2143.I(B). Regarding claim 8, Park in view of Park2 teaches (Park2, Fig. 1) the stack chip package of claim 6, wherein the control chip has a size smaller than a size of the semiconductor chips in the first stack structure (710 has a shorter width than 301) and a support (730, [0063]) is arranged in the space between the first stack structure and the package substrate ([0063]) but does not explicitly teach wherein the control chip is positioned adjacent to the first sidewall portion of the first stack structure to form a space between the first stack structure and the package substrate. The specification of the instant application is silent to criticality of the positioning of the control chip "adjacent to the first sidewall portion of the first stack structure," and therefore fails to teach criticality of the claimed feature. Park2 teaches a stack chip package having a control chip underneath the first stack structure, in addition to a support arranged in the space between the first stack structure and the package substrate. Changes in shape and size are known in the art, and it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Park2 to move the control chip from the center of the semiconductor stack to be adjacent with the first sidewall with the predictable result of providing a control device below the stack. See MPEP 2144.04.IV.A. Regarding claim 9, Park in view of Park2 teaches the stack chip package of claim 6, wherein a height from the package substrate to an uppermost portion of the first stack structure is substantially the same as a height from the package substrate to an uppermost portion of the second stack structure. Park teaches wherein the stack chip structures can have the same structure, therefore the height from the package substrate to an uppermost portion of the first stack structure must necessarily be the same as a height from the package substrate to an uppermost of the second stack structure. Regarding claim 10, Park in view of Park2 teaches (Park, Annotated Fig. 1D below) the stack chip package of claim 1, wherein the adjacent first (P1) and second (P2) protrusions are spaced apart from each other by a first gap (G1), and wherein the first concave portion (C1) and the second protrusion (P2) facing each other and first protrusion (P1) and the second concave portion (C2) facing each other are spaced apart from each other by a second gap (G2), wherein the second gap is wider than the first gap (see Figure). PNG media_image3.png 343 397 media_image3.png Greyscale Regarding claim 11, Park in view of Park2 teaches (Park, Annotated Fig. 1D below) the stack chip package of claim 1, wherein the adjacent first and second protrusion are spaced apart from each other by a gap (G1), the first concave portion and the second protrusion facing each other are spaced apart from each other by the gap (G1), and the first protrusion and the second concave portion facing each other are spaced apart from each other by the gap (G1). The distance between the first concave portion and the second protrusion (G3) and the distance between the first protrusion and the second concave portion (G2) are at least the distance of the gap G1. PNG media_image4.png 413 397 media_image4.png Greyscale Regarding claim 13, Park in view of Park2 teaches (Park Fig. 1D) the stack chip package of claim 1, further comprising a connection member (415a, 425a, [0102-0103]) configured to connect the semiconductor chips of the first stack structure (100) with each other, the semiconductor chips of the second stack structure (200) with each other, the semiconductor chips of the first stack structure with the package substrate (300, [0103]), and the semiconductor chips of the second stack structure with the package substrate (300, [0102]) Regarding claim 16, Park in view of Park2 teaches (Fig. 1D) the stack chip package of claim 1, wherein numbers of the semiconductor chips in the first stack structure are substantially equal to the number of semiconductor chips in the second stack structure. See Figure . 07-22-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2 as applied to claim 1 above, and further in view of Harada et al. (US PGPub 2012/0049376; herein known as Harada) . Regarding claim 5, Park in view of Park2 teaches the stack chip package of claim 3, wherein the insulating adhesive layer (Park2, Fig. 5, 350, [0041]) attached to the semiconductor chip (330, [0040]) has a thickness thicker ([0041]) than a thickness of the insulating adhesive layer (Park2, Fig. 5, 355, [0041]) attached to other semiconductor chips (Park2, Fig. 5, 301, [0041]), but does not explicitly teach wherein at least one of the first stack structure and the second stack structure comprises a semiconductor chip having a relatively thin thickness, and wherein the insulating adhesive layer attached to the semiconductor chip having the relatively thin thickness has a thickness thicker than a thickness of the insulating adhesive layer attached to other semiconductor chips. The specification of the instant application fails to teach criticality of the thickness of any specific semiconductor chip and of the thickness of its respective insulating adhesive layer, instead teaching multiple suitable embodiments wherein the thicknesses of die and adhesive layers are equal, or different. Harada teaches adjustment of the thickness of die and adhesive layers as a result effective variable affecting the accumulated position error of die stacks ([0031]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include wherein at least one of the first stack structure and the second stack structure comprises a semiconductor chip having a relatively thin thickness, and wherein the insulating adhesive layer attached to the semiconductor chip having the relatively thin thickness has a thickness thicker than a thickness of the insulating adhesive layer attached to other semiconductor chips as a result effective variable, in order to minimize the accumulated position error of the stacked die (Harada, [0031]). See MPEP 2143.I(D) . 07-22-aia AIA Claim s 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2 as applied to claim s 1 and 13 above, and further in view of Tai et al. (US PGPub 2022/0068877; herein known as Tai) . Regarding claim 8, Park in view of Park2 teaches the stack chip package of claim 6, but does not explicitly teach wherein a height from the package substrate to an uppermost portion of the first stack structure is higher than a height from the package substrate to an uppermost portion of the second stack structure. Tai teaches (Fig. 3B) wherein a height from the package substrate (301, [0033]) to an uppermost portion of the first stack structure (303b, [0033]) is higher than a height from the package substrate to an uppermost portion of the second stack structure (302, [0033]). Because Park in view of Park2 and Tai are directed toward stack chip packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Park2 and Tai to include wherein a height from the package substrate to an uppermost portion of the first stack structure is higher than a height from the package substrate to an uppermost portion of the second stack structure in order to allow for overlap between chip stacks to overcome the limitation of surface area on the substrate (Tai, [0025]). Regarding claim 14, Park in view of Park2 teaches the stack chip package of claim 13, wherein the connection member comprises at least one of a bonding wire, but does not explicitly teach wherein the connection member comprises at least one of a through silicon via (TSV). The specification of the instant application does not teach criticality of use of a TSV versus a bonding wire, instead teaching them both as suitable options for providing electrical connection. Park in view of Park2 teaches use of bonding wires to connect adjacent stacked die for the purpose of providing electrical connection. Tai teaches wherein use of interconnect technologies (e.g. TSVs) is interchangeable, for the purpose of providing electrical connection between adjacent stacked die ([0045]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the TSV of Tai in the device of Park in view of Park2 for the predictable result of providing electrical connection between stacked die. See MPEP 2143.I(A) . 07-22-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2 as applied to claim 1 above, and further in view of Kim et al. (US PGPub 2021/0057379; herein known as Kim) . Regarding claim 12, Park in view of Park2 teaches the stack chip package of claim 1, but does not explicitly teach further comprising an air gap layer positioned between the first sidewall portion of the first stack structure and the third sidewall portion of the second stack structure. Kim teaches (annotated Fig. 9A below) further comprising an air gap layer (AG) positioned between the first sidewall portion (S1) of the first stack structure (St1) and the third sidewall portion (S3) of the second stack structure (St2). PNG media_image5.png 355 507 media_image5.png Greyscale Because Park in view of Park2 and Kim are directed toward stack chip packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Park2 and of Kim to include further comprising an air gap layer positioned between the first sidewall portion of the first stack structure and the third sidewall portion of the second stack structure in order to ensure that bond wires do not experience sweeping during fill processes (Kim, [0038]) . 07-22-aia AIA Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2 as applied to claim 1 above, and further in view of Lee et al. (US PGPub 2018/0342481; herein known as Lee) . Regarding claim 15, Park in view of Park2 teaches the stack chip package of claim 1, but does not explicitly teach further comprising a gap-forming layer interposed between the semiconductor chips of the first stack structure and/or between the semiconductor chips of the second stack structure to secure thicknesses of the first and second concave portions and thicknesses of the first and second protrusions. Lee teaches (not pictured) a gap-forming layer ([0037]) interposed between the semiconductor chips (210, [0037]) of the first stack structure to secure thicknesses of the first and second concave portions and thicknesses of the first and second protrusions. Examiner notes that because Park in view of Park2 and Lee teaches the claimed structure, it must necessarily “secure thicknesses of the first and second concave portions and thicknesses of the first and second protrusions,” and that this limitation is not interpreted to place a further physical constraint on the claim. Because Park in view of Park2 and Lee are both directed toward stack chip packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Park2 and of Lee to include further comprising a gap-forming layer interposed between the semiconductor chips to secure thicknesses of the first and second concave portions and thicknesses of the first and second protrusions in order to compensate height difference between the first and second chip stacks (Lee, [0037]) . 07-21-aia AIA Claim s 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2, further in view of Gillingham et al. (US PGPub 2012/0056335) . Regarding claim 17, Park teaches (annotated Fig. 1D below) a stack chip package comprising: a package substrate (300, [0087]); a first stack structure (700, [0044]) including a plurality of semiconductor chips (702A-D, [0044]) stacked on the package substrate, the first stack structure including a first sidewall portion (right side) and a second sidewall portion (left side), and the first sidewall portion including a first concave portion (C1) and a first protrusion (P1) alternately stacked; a second stack structure (200, [0087]) arranged at one side of the first sidewall portion (S1) of the first stack structure, the second stack structure including a plurality of semiconductor chips (201, [0087]) stacked on the package substrate, the second stack structure including a third sidewall portion (S3) facing the first sidewall portion and a fourth sidewall portion (S4), and the third sidewall portion including a second concave portion (C2) and a second protrusion (P2) alternately stacked; wherein the first concave portion (C1) of the first stack structure (100) faces the second protrusion (P2) of the second stack structure (200) and the first protrusion (P1) of the first stack structure faces the second concave portion (C2) of the second stack structure. PNG media_image1.png 380 411 media_image1.png Greyscale Park does not explicitly teach a passive element integrated on the package substrate outside the second sidewall portion of the first stack structure and/or the fourth sidewall portion of the second stack structure. Park2 teaches (Fig. 1) a passive element (610, [0025]) integrated on the package substrate (200, [0022]) outside the second sidewall portion (outer wall) of the first stack structure (300, [0022]). Because Park and Park2 are both directed toward stack chip packages, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park and of Park2 to include a passive element integrated on the package substrate outside the second sidewall portion of the first stack structure in order to provide improvement of electrical characteristics and reliability of signal characteristics of the stack package (Park2, [0025]). Park in view of Park2 does not explicitly teach a first stack structure, stacked on the package substrate in a zigzag pattern to expose edge pads of each of the semiconductor chip, and the second stack structure stacked on the package substrate in a zigzag pattern to expose edge pads of the semiconductor chips. The instant application teaches multiple embodiments of stacked chips, therefore the exact configuration of the chip stack package must necessarily be non-critical. Park in view of Park2 teaches multiple configurations of chip stacking, with the function of providing bonding areas for the chips contained in the stacks (Park, [0023]), having the predictable result of enabling chip stack packaging where stacked chips can be connected to each other and to a substrate. Gillingham teaches (Fig. 7) a stack structure (700, [0044]), stacked on the package substrate in a zigzag pattern (see figure) to expose edge pads (704, [0044) of each of the semiconductor chips, with the predictable result of enabling a chip stack package where stacked chips are connected to each other and to a substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use simple substitution of the chip stack structure of Gillingham in the stacks of Park in view of Park2 for the predictable result of enabling a chip stack package where stacked chips are connected to each other and to a substrate (Gillingham, [0044]). See MPEP 2143.I(B). PNG media_image6.png 211 590 media_image6.png Greyscale Regarding claim 18, Park in view of Park2 and Gillingham teaches (annotated Fig. 7 below) wherein the first sidewall portion (right side) of even numbered semiconductor chips (702B,D) among the plurality of the semiconductor chips (702A-D) in the first stack structure is protruded from the first sidewall portion of odd numbered semiconductor chips (702A,C) among the plurality of the semiconductor chips in the first stack structure (Park, Fig. 1D, 100) toward the second stack structure (Park, Fig. 1D, 200) to form the first concave portions (C1, C3) at the first sidewall portions of the odd numbered semiconductor chips and the first protrusions (P1, P4) at the first sidewall portions of the even numbered semiconductor chips. Park2 teaches wherein a support (710) is inserted into the first stack structure (Park, Fig. 1D, 100). Examiner notes that the claim limitation “to face the first concave portion and the second protrusion to each other and the first protrusion and the second concave portion to each other” comprises a functional limitation, and that the teachings of Park in view of Park2 and Gillingham teach the structure as required by the product claim limitations, and therefore must necessarily teach the function to face the first concave portion and the second protrusion to each other and the first protrusion and the second concave portion to each other. PNG media_image7.png 240 612 media_image7.png Greyscale Park in view of Park2 and Gillingham does not explicitly teach wherein the third sidewall portion of even numbered semiconductor chips among the plurality of the semiconductor chips in the second stack structure is protruded from the third sidewall portion of odd numbered semiconductor chips among the plurality of the semiconductor chips in the second stack structure toward the first stack structure to form the second concave portions at the third sidewall portions of the odd numbered semiconductor chips and the second protrusions at the third sidewall portions of the even numbered semiconductor chips. Park teaches separate embodiments wherein the concave and protruding portions can be either the odd or even numbered semiconductor chips (Fig. 3B, 100b, 200b) as an optional configuration chosen based on design considerations, for the predictable result of exposing bond pads in a stack chip package for electrical connection to other chips and the substrate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Park in view of Park2 and Gillingham to include wherein the third sidewall portion of even numbered semiconductor chips among the plurality of the semiconductor chips in the second stack structure is protruded from the third sidewall portion of odd numbered semiconductor chips among the plurality of the semiconductor chips in the second stack structure toward the first stack structure to form the second concave portions at the third sidewall portions of the odd numbered semiconductor chips and the second protrusions at the third sidewall portions of the even numbered semiconductor chips for the predictable result of exposing bond pads in a stack chip package for electrical connection to other chips and the substrate. Regarding claim 19, Park in view of Park2 and Gillingham teaches ((Annotated Fig. 7 below, the annotations on the left-hand side of the figure are included to clarify the third sidewall of the second chip stack, were it to be shown) the stack chip package of claim 17, wherein a distance between the first concave portion (C1) and the second protrusion facing each other is substantially the same as a distance between the first protrusion (P2) and the second concave portion facing each other. The stack structure of Gillingham, taught into the device of Park in view of Park2, as described in the rejection of claim 17, would necessarily have a gap between the first concave portion and the second protrusion equal to 3d plus or minus the chosen horizontal offset of the chip stack. This would be the same as the distance between first protrusion and the second concave portion facing each other, as each chip is offset from its vertically adjacent chip by a distance d . PNG media_image8.png 240 691 media_image8.png Greyscale 07-22-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park2 and Gillingham as applied to claim 17 above, and further in view of Tai . Regarding claim 20, Park in view of Park2 and Gillingham teaches (Annotated Fig. 7 below, the annotations on the left-hand side of the figure are included to clarify the third sidewall of the second chip stack, were it to be shown) the stack chip package of claim 17, wherein a distance between the first concave portion (C1) and the second protrusion (P1) facing each other, a distance between the first protrusion (P2) and the second concave portion (C2) facing each other, but does not explicitly teach and a distance between the adjacent first and second protrusions are substantially equal to each other. PNG media_image8.png 240 691 media_image8.png Greyscale The specification of the instant application teaches multiple offset values (L2) between adjacent first and second protrusions, and therefore necessarily teaches that the value is not critical. Tai teaches (Fig. 3A) wherein the choice of offset between adjacent first and second protrusions is a result effective variable impacting the surface area space of the substrate required for die mounting. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Park in view of Park2 and Gillingham to choose an offset between adjacent first and second protrusions to match that of the distance between that of the first concave portion and the second protrusion, and between the first protrusion and the second concave portion in order to reduce the required substrate area for die mounting (Tai, [0025]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY N FARMER whose telephone number is (703)756-1472. The examiner can normally be reached Monday-Friday 7:30-5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EMILY FARMER/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/645,374 Page 2 Art Unit: 2812 Application/Control Number: 18/645,374 Page 3 Art Unit: 2812 Application/Control Number: 18/645,374 Page 4 Art Unit: 2812 Application/Control Number: 18/645,374 Page 5 Art Unit: 2812 Application/Control Number: 18/645,374 Page 6 Art Unit: 2812 Application/Control Number: 18/645,374 Page 7 Art Unit: 2812 Application/Control Number: 18/645,374 Page 8 Art Unit: 2812 Application/Control Number: 18/645,374 Page 9 Art Unit: 2812 Application/Control Number: 18/645,374 Page 10 Art Unit: 2812 Application/Control Number: 18/645,374 Page 11 Art Unit: 2812 Application/Control Number: 18/645,374 Page 12 Art Unit: 2812 Application/Control Number: 18/645,374 Page 13 Art Unit: 2812 Application/Control Number: 18/645,374 Page 14 Art Unit: 2812 Application/Control Number: 18/645,374 Page 15 Art Unit: 2812 Application/Control Number: 18/645,374 Page 16 Art Unit: 2812 Application/Control Number: 18/645,374 Page 17 Art Unit: 2812 Application/Control Number: 18/645,374 Page 18 Art Unit: 2812 Application/Control Number: 18/645,374 Page 19 Art Unit: 2812 Application/Control Number: 18/645,374 Page 20 Art Unit: 2812 Application/Control Number: 18/645,374 Page 21 Art Unit: 2812 Application/Control Number: 18/645,374 Page 22 Art Unit: 2812
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