Prosecution Insights
Last updated: April 19, 2026
Application No. 18/645,398

SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

Final Rejection §103
Filed
Apr 25, 2024
Examiner
HUANG, MIN
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK Hynix Inc.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
2y 2m
To Grant
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allow Rate
743 granted / 824 resolved
+22.2% vs TC avg
Moderate +10% lift
Without
With
+9.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
18 currently pending
Career history
842
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
54.3%
+14.3% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 824 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Allowable Subject Matter Claim 4-8, 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (PGPUB 20210166774), hereinafter as Cha, in view of Yoon et al. (PGPUB 20180204624), hereinafter as Yoon. Regarding claim 1, Cha teaches controller for a semiconductor memory device including a plurality of memory blocks, the controller comprising: a read-history table storage (Fig. 1, HB, and [0082]) configured to store a read-history table including read voltages used in at least two previously read-passed read operations on a select memory block among the plurality of memory blocks (Fig 6A, SBN-block, HRL1-3 history read levels); and a read voltage controller (Fig 1, controller 110) configured to control the memory device to perform a read operation using the read voltages stored in the read-history table (Fig 15), update the read-history table based (Fig 6A), but not expressly an optimum read voltage search component configured to search a valley of a threshold voltage distribution based on a plurality of reference read voltages; Yoon teaches an optimum read voltage search component configured to search a valley of a threshold voltage distribution based on a plurality of reference read voltages ([0081-83]). Since Yoon and Cha are both from the same field of semiconductor memory device, the purpose disclosed by Yoon would have been recognized in the pertinent art of Cha. It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to search an optimum read voltage as in Yoon into Cha for the purpose of reading data out the memory device. Regarding claim 2, Cha teaches an error correction block configured to perform an error correction operation on first data provided from the memory device as a result of the read operation using a default read voltage (Fig 14A, S121, and error correction S114-116-123). Regarding claim 3, Cha and Yoon teach when the error correction operation on the first data fails, the read voltage controller controls the memory device to perform the read operation using the first read voltage, which is most recently updated read voltage among the read voltages used in the at least two previously read-passed read operation (Cha Fig 6A, and Yoon [0081]). Regarding claim 9, Cha teaches a memory system, comprising: a memory device configured to include a plurality of memory blocks (Fig 1, SB); a controller configured to receive a read request (Fig 15) for data in a select memory block among the plurality of memory blocks from a host and to control the memory device to read data corresponding to the read request using a read-history table including read voltages used in at least two previously read-passed read operations on the select memory block (Fig 6A), and update the read-history table (Fig 6A) but not expressly search a valley of a threshold voltage distribution based on a plurality of reference read voltages; Yoon teaches to search a valley of a threshold voltage distribution based on a plurality of reference read voltages ([0081-83]). The reason for combining the references used in rejection of claim 1 applies. Regarding claim 10, Cha and Yoon teach to store the read-history table including read voltages used in at least two previously read-passed read operations on a select memory block among the plurality of memory blocks (Cha Fig 6A and Yoon [0081]); control the memory device to perform a read operation using the read voltages stored in the read-history table (Fig 15); and perform an error correction operation on first data provided from the memory device as a result of the read operation using a default read voltage (Fig 14A). Regarding claim 11, Cha and Yoon teach when the error correction operation on the first data fails, the controller is configured to control the memory device to perform the read operation using the first read voltage (Fig 15, S360), which is most recently updated read voltage among the read voltages used in the at least two previously read-passed read operation (Cha Fig 6A, and Yoon [0081]). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MIN HUANG/Primary Examiner, Art Unit 2827
Read full office action

Prosecution Timeline

Apr 25, 2024
Application Filed
Oct 09, 2025
Non-Final Rejection — §103
Jan 12, 2026
Response Filed
Jan 19, 2026
Final Rejection — §103
Mar 26, 2026
Applicant Interview (Telephonic)
Mar 26, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.9%)
2y 2m
Median Time to Grant
Moderate
PTA Risk
Based on 824 resolved cases by this examiner. Grant probability derived from career allow rate.

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