Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 04/25/2024.
Drawings
The drawings are objected to because of the following informalities. Regarding Fig. 1, the unlabeled rectangular box(es), i.e. box 28, shown in the drawings should be provided with descriptive text labels. Regarding Fig. 6, the unlabeled rectangular box(es), i.e. box 242, shown in the drawings should be provided with descriptive text labels.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 12 and 16 are objected to because of the following informalities: Regarding claim 12, in line 12, “the first control output” appears that it should read as “a first control output”, because of antecedent basis;
in line 17, “the second control output” appears that it should read as “a second control output”, because of antecedent basis.
Regarding claim 16, in line 3, “and to select the first signal” appears that it should read as “and to control the multiplexer to select the first signal”, because claim 12 recites the multiplexer as the element that provides the first signal and the second signal. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US Patent Application Publication US 2019/0302819 A1) in view of Setiawan et al. (US Patent Application Publication US 2021/0255653 A1, hereinafter “Setiawan”).
Regarding claim 1, Hu discloses (see Fig. 3) a device (multiple-mode voltage regulator 300) comprising: an amplifier (error amplifier 308a) having a first input terminal (first input of 308a), a second input terminal (second input of 308a), and an output terminal (output of 308a), the first input terminal configured to receive a reference voltage source (Vref); a select circuit (multiplexer 322a) having a first input terminal (input of 322a coupled to Vout at node 306), a second input terminal (input of 322a coupled to the output of replica pass transistor 316a), and a select circuit output terminal (output of 322a) that is electrically coupled to the second input terminal of the amplifier (output of 322a is coupled to the second input of 308a, see [0028] of Hu “the second input is selectively coupled via a multiplexer 322”); and a loop control circuit (pass transistor 310a and replica device 314a) having an input electrically coupled to the output terminal of the amplifier (gate of 310a and gate of 316a are coupled to the output of 308a), a first control output (node 306) electrically coupled to the first input terminal (node 306 is coupled to the input of 322a), and a second control output (output of replica pass transistor 316a) electrically coupled to the second input terminal (output of 316a is coupled to the input of 322a), wherein the select circuit is configured to provide a first signal from the first control output to the second input terminal in a first mode of operation and a second signal from the second control output to the second input terminal in a second mode of operation (transition logic 324a controls 322a to select the output of 316a during the transition period and to select Vout at node 306 at the end of the transition period).
Hu does not disclose an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive a reference voltage source; a select circuit output terminal that is electrically coupled to the negative input terminal of the amplifier; and wherein the select circuit is configured to provide a first signal from the first control output to the negative input terminal in standby mode and a second signal from the second control output to the negative input terminal in nap mode.
However, Setiawan teaches (see Fig. 3) an amplifier (transconductor 320) having a positive input terminal (positive input terminal of 320), a negative input terminal (negative input terminal of 320), and an output terminal (output of 320), the positive input terminal configured to receive a reference voltage source (positive input terminal of 320 receives vref from selection circuit 310 coupled to the resistor ladder R1-R4 between Vrefg and vssa); a select circuit output terminal that is electrically coupled to the negative input terminal of the amplifier (output of selection circuit 350 is coupled to the negative input terminal of 320, see [0040] of Setiawan “a selection circuit 350 selectively provides a feedback voltage to transconductor 320”); and wherein the select circuit is configured to provide a first signal from the first control output to the negative input terminal in standby mode (selection circuit 350 provides vfb_main, sensed from the regulated voltage vddd, to the negative input terminal of 320 in the normal operating mode) and a second signal from the second control output to the negative input terminal in nap mode (selection circuit 350 provides vfb_rep from replica loop 330 to the negative input terminal of 320 in the mode associated with the snooze mode, see [0023] of Setiawan “This snooze mode may be a low power mode”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu to include an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive a reference voltage source, a select circuit output terminal that is electrically coupled to the negative input terminal of the amplifier, and the select circuit configured to provide a first signal from the first control output to the negative input terminal in standby mode and a second signal from the second control output to the negative input terminal in nap mode, as taught by Setiawan, because it can help maintain a negative feedback path that regulates the output voltage toward the reference voltage, and because it can help reduce the power consumption of the device when the device is placed in a nap mode.
Regarding claim 2, Hu does not disclose wherein the positive input terminal is configured to receive a standby reference voltage in the standby mode and a nap reference voltage in the nap mode.
However, Setiawan teaches (see Fig. 3) wherein the positive input terminal is configured to receive a standby reference voltage in the standby mode (positive input terminal of transconductor 320 receives a first one of the reference voltage levels vref_1-vref_n selected by multiplexer 310) and a nap reference voltage in the nap mode (positive input terminal of 320 receives a second one of the reference voltage levels vref_1-vref_n selected by multiplexer 310, see [0035] of Setiawan “Depending upon mode of operation, a selected one of multiple reference voltage levels”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu wherein the positive input terminal is configured to receive a standby reference voltage in the standby mode and a nap reference voltage in the nap mode, as taught by Setiawan, because it can help reduce the power consumption of the device in the nap mode.
Regarding claim 3, Hu discloses (see Fig. 3) wherein the select circuit has a select input (select input of multiplexer 322a) that receives an input signal for switching between providing the first signal and the second signal (transition logic 324a provides the transition signal to the select input of 322a, see [0031] of Hu “the output of the transition signal may be used to control the input selection”).
Hu does not disclose wherein the select circuit has a select input that receives a nap input signal for switching between providing the first signal in the standby mode and the second signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 5) wherein the select circuit has a select input (select input of selection circuit 350 that receives sw_fb) that receives a nap input signal (snooze signal 510 provided by control circuitry of the integrated circuit, see [0048] of Setiawan “a snooze signal 510 may be used to cause transitions between the different modes”, Examiner’s Note: Fig. 5 of Setiawan illustrates the operation of the voltage regulator of Fig. 3) for switching between providing the first signal in the standby mode and the second signal in the nap mode (selection circuit 350 provides vfb_main in the normal operating mode and vfb_rep in the mode associated with the snooze mode).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu wherein the select circuit has a select input that receives a nap input signal for switching between providing the first signal in the standby mode and the second signal in the nap mode, as taught by Setiawan, because it can help switch the device between the standby mode and the nap mode in response to a single signal that indicates the nap mode.
Regarding claim 4, Hu does not disclose a device control circuit configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode and to control the select circuit to select the first signal in the standby mode and the second signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 7) a device control circuit (regulator control circuit 725 of digital core 720, see [0055] of Setiawan “a regulator control circuit 725 which may provide control signals to control operation”, Examiner’s Note: Fig. 7 of Setiawan illustrates an integrated circuit in which the power circuitry 740 includes the voltage regulator of Fig. 3) configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode (725 provides the control signal trim_hdreglv[2:0] that causes multiplexer 310 to select one of the reference voltage levels vref_1-vref_n depending upon the mode of operation) and to control the select circuit to select the first signal in the standby mode and the second signal in the nap mode (725 provides the feedback control signal that causes selection circuit 350 to select vfb_main or vfb_rep).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu to include a device control circuit configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode and to control the select circuit to select the first signal in the standby mode and the second signal in the nap mode, as taught by Setiawan, because it can help coordinate the reference voltage and the selected signal from a single determination of the operating mode of the device.
Regarding claim 5, Hu discloses (see Fig. 3) wherein the select circuit includes a multiplexer (multiplexer 322a, see [0028] of Hu “the second input is selectively coupled via a multiplexer 322”) having the first input terminal (input of 322a coupled to Vout at node 306), the second input terminal (input of 322a coupled to the output of replica pass transistor 316a), and the select circuit output terminal (output of 322a).
Hu does not disclose the select circuit output terminal that is electrically coupled to the negative input terminal of the amplifier.
However, Setiawan teaches (see Fig. 3) the select circuit output terminal that is electrically coupled to the negative input terminal of the amplifier (output of selection circuit 350 is coupled to the negative input terminal of transconductor 320).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Hu wherein the select circuit output terminal is electrically coupled to the negative input terminal of the amplifier, as taught by Setiawan, because it can help maintain a negative feedback path that regulates the output voltage toward the reference voltage.
Regarding claim 6, Hu discloses (see Fig. 3 and Fig. 5) a resistor and capacitor circuit (RC circuit comprising capacitor 505 and resistor 507, see [0034] of Hu “A RC circuit comprising a capacitor 505 and a resistor 507”, Examiner’s Note: Fig. 5 of Hu illustrates an example implementation of the error amplifier 308 of Fig. 3) electrically connected to the output terminal of the amplifier (the RC circuit is coupled to the output of error amplifier circuitry 502 of error amplifier 308).
Regarding claim 7, Hu discloses (see Fig. 3) wherein the loop control circuit includes a first pass transistor (pass transistor 310a) having a first gate (gate of 310a) electrically coupled to the output terminal of the amplifier (gate of 310a is coupled to the output of error amplifier 308a), and a second pass transistor (replica pass transistor 316a) having a second gate (gate of 316a) electrically coupled to the output terminal of the amplifier (gate of 316a is coupled to the output of error amplifier 308a, see [0029] of Hu “the error amplifier 308 controls the gate bias”).
Regarding claim 8, Hu discloses (see Fig. 3) wherein the first pass transistor has a first drain/source path (drain/source path of pass transistor 310a) that includes a first end (drain of 310a) configured to receive an input voltage source (voltage supply 311a, see [0028] of Hu “a pass transistor 310 coupled to a voltage supply 311 and a current source 312”) and a second end (source of 310a) electrically coupled to the first control output (source of 310a is coupled to node 306 at which Vout is provided).
Regarding claim 9, Hu discloses (see Fig. 3) wherein the second pass transistor has a second drain/source path (drain/source path of replica pass transistor 316a) that includes a third end (drain of 316a) configured to receive the input voltage source (voltage supply 311a) and a fourth end (source of 316a) electrically coupled to the second control output (source of 316a is coupled to the input of multiplexer 322a, see [0029] of Hu “the voltage output (i.e., source voltage) of the replica pass transistor 316”).
Regarding claim 10, Hu discloses (see Fig. 3) wherein the first drain/source path is electrically connected to a first current source (current source 312a is connected to the source of pass transistor 310a) and the second drain/source path is electrically connected to a second current source (bias current transistor 320a, in combination with resistor 318a, is connected to the source of replica pass transistor 316a and provides a bias current for the replica pass transistor 316a, see [0028] of Hu “replaced with a current source”, Examiner’s Note: Hu discloses that the bias current transistor 320 may alternatively be implemented as a current source).
Regarding claim 11, Hu discloses (see Fig. 3) wherein each of the first pass transistor and the second pass transistor is an N-type metal-oxide semiconductor (NMOS) transistor (pass transistor 310a and replica pass transistor 316a each have one terminal connected to voltage supply 311a and an opposite terminal that provides the voltage output, and each is illustrated with the same transistor symbol as bias current transistor 320a whose source is connected to ground, see [0029] of Hu “the voltage output (i.e., source voltage) of the replica pass transistor 316”, Examiner’s Note: because the terminal of the replica pass transistor 316a that provides the voltage output is the source and the opposite terminal is connected to voltage supply 311a, the replica pass transistor 316a is an N-type metal-oxide semiconductor transistor).
Regarding claim 12, Hu discloses (see Fig. 3) a low dropout regulator device (voltage regulator 302 configured as a low dropout (LDO) regulator, see [0028] of Hu “each voltage regulator 302, 304 is configured as a low dropout (LDO) regulator”) comprising: an amplifier (error amplifier 308a) having a first input terminal (first input of 308a), a second input terminal (second input of 308a), and an output terminal (output of 308a), the first input terminal configured to receive a reference voltage source (Vref); a multiplexer (multiplexer 322a) having a first input terminal (input of 322a coupled to Vout at node 306), a second input terminal (input of 322a coupled to the output of replica pass transistor 316a), and a multiplexer output terminal (output of 322a) that is electrically coupled to the second input terminal of the amplifier (output of 322a is coupled to the second input of 308a); and a loop control circuit (pass transistor 310a and replica device 314a) including: a first pass transistor (pass transistor 310a) having a first gate (gate of 310a) electrically coupled to the output terminal of the amplifier (gate of 310a is coupled to the output of 308a) and a first drain/source path (drain/source path of 310a) that includes a first end (drain of 310a) configured to receive an input voltage source (voltage supply 311a) and a second end (source of 310a) electrically coupled to the first control output (node 306) that is electrically coupled to the first input terminal (node 306 is coupled to the input of 322a); and a second pass transistor (replica pass transistor 316a) having a second gate (gate of 316a) electrically coupled to the output terminal of the amplifier (gate of 316a is coupled to the output of 308a) and a second drain/source path (drain/source path of 316a) that includes a third end (drain of 316a) configured to receive the input voltage source (voltage supply 311a) and a fourth end (source of 316a) electrically coupled to the second control output (output of 316a) that is electrically coupled to the second input terminal (output of 316a is coupled to the input of 322a), wherein the multiplexer is configured to provide a first signal from the first control output to the second input terminal in a first mode of operation and a second signal from the second control output to the second input terminal in a second mode of operation (transition logic 324a controls 322a to select the output of 316a during the transition period and to select Vout at node 306 at the end of the transition period).
Hu does not disclose an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive a reference voltage source; a multiplexer output terminal that is electrically coupled to the negative input terminal of the amplifier; and wherein the multiplexer is configured to provide a first signal from the first control output to the negative input terminal in standby mode and a second signal from the second control output to the negative input terminal in nap mode.
However, Setiawan teaches (see Fig. 3) an amplifier (transconductor 320) having a positive input terminal (positive input terminal of 320), a negative input terminal (negative input terminal of 320), and an output terminal (output of 320), the positive input terminal configured to receive a reference voltage source (positive input terminal of 320 receives vref from selection circuit 310, see [0035] of Setiawan “the reference voltage (vref) is received from a selection circuit 310”); a multiplexer output terminal that is electrically coupled to the negative input terminal of the amplifier (output of selection circuit 350 is coupled to the negative input terminal of 320); and wherein the multiplexer is configured to provide a first signal from the first control output to the negative input terminal in standby mode (selection circuit 350 provides vfb_main, sensed from the regulated voltage vddd, to the negative input terminal of 320 in the normal operating mode) and a second signal from the second control output to the negative input terminal in nap mode (selection circuit 350 provides vfb_rep from replica loop 330 to the negative input terminal of 320 in the mode associated with the snooze mode).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low dropout regulator device of Hu to include an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive a reference voltage source, a multiplexer output terminal that is electrically coupled to the negative input terminal of the amplifier, and the multiplexer configured to provide a first signal from the first control output to the negative input terminal in standby mode and a second signal from the second control output to the negative input terminal in nap mode, as taught by Setiawan, because it can help maintain a negative feedback path that regulates the output voltage toward the reference voltage, and because it can help reduce the power consumption of the device when the device is placed in a nap mode.
Regarding claim 13, Hu discloses (see Fig. 3) wherein the first drain/source path is electrically connected to a first current source (current source 312a is connected to the source of pass transistor 310a) and the second drain/source path is electrically connected to a second current source (bias current transistor 320a, in combination with resistor 318a, is connected to the source of replica pass transistor 316a and provides a bias current for the replica pass transistor 316a, see [0028] of Hu “replaced with a current source”, Examiner’s Note: Hu discloses that the bias current transistor 320 may alternatively be implemented as a current source).
Regarding claim 14, Hu does not disclose wherein the positive input terminal is configured to receive from the reference voltage source a standby reference voltage in the standby mode and a nap reference voltage in the nap mode.
However, Setiawan teaches (see Fig. 3) wherein the positive input terminal is configured to receive from the reference voltage source a standby reference voltage in the standby mode (positive input terminal of transconductor 320 receives from the resistor ladder R1-R4 a first one of the reference voltage levels vref_1-vref_n selected by multiplexer 310) and a nap reference voltage in the nap mode (positive input terminal of 320 receives from the resistor ladder R1-R4 a second one of the reference voltage levels vref_1-vref_n selected by multiplexer 310, see [0035] of Setiawan “Depending upon mode of operation, a selected one of multiple reference voltage levels”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low dropout regulator device of Hu wherein the positive input terminal is configured to receive from the reference voltage source a standby reference voltage in the standby mode and a nap reference voltage in the nap mode, as taught by Setiawan, because it can help reduce the power consumption of the device in the nap mode.
Regarding claim 15, Hu discloses (see Fig. 3) wherein the multiplexer has a select input (select input of multiplexer 322a) that receives an input signal for switching between providing the first signal and the second signal (transition logic 324a provides the transition signal to the select input of 322a, see [0031] of Hu “the output of the transition signal may be used to control the input selection”).
Hu does not disclose wherein the multiplexer has a select input that receives a nap input signal for switching between providing the first signal in the standby mode and the second signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 5) wherein the multiplexer has a select input (select input of selection circuit 350 that receives sw_fb) that receives a nap input signal (snooze signal 510 provided by control circuitry of the integrated circuit, see [0048] of Setiawan “a snooze signal 510 may be used to cause transitions between the different modes”) for switching between providing the first signal in the standby mode and the second signal in the nap mode (selection circuit 350 provides vfb_main in the normal operating mode and vfb_rep in the mode associated with the snooze mode).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low dropout regulator device of Hu wherein the multiplexer has a select input that receives a nap input signal for switching between providing the first signal in the standby mode and the second signal in the nap mode, as taught by Setiawan, because it can help switch the device between the standby mode and the nap mode in response to a single signal that indicates the nap mode.
Regarding claim 16, Hu does not disclose a device control circuit configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode and to select the first signal in the standby mode and the second signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 7) a device control circuit (regulator control circuit 725 of digital core 720) configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode (725 provides the control signal trim_hdreglv[2:0] that causes multiplexer 310 to select one of the reference voltage levels vref_1-vref_n depending upon the mode of operation) and to select the first signal in the standby mode and the second signal in the nap mode (725 provides the feedback control signal that causes selection circuit 350 to select vfb_main or vfb_rep, see [0041] of Setiawan “a feedback control signal is provided”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the low dropout regulator device of Hu to include a device control circuit configured to control the reference voltage source to provide a standby reference voltage in the standby mode and a nap reference voltage in the nap mode and to select the first signal in the standby mode and the second signal in the nap mode, as taught by Setiawan, because it can help coordinate the reference voltage and the selected signal from a single determination of the operating mode of the device.
Regarding claim 17, Hu discloses (see Fig. 3) a method of operating a low dropout (LDO) regulator device (voltage regulator 302 configured as a low dropout (LDO) regulator), the method including: providing, to a terminal of an amplifier, a reference voltage (Vref is provided to the first input of error amplifier 308a); selecting, by a select circuit (multiplexer 322a), a first loop control signal from a loop control circuit (Vout at node 306 provided by pass transistor 310a) and a second loop control signal from the loop control circuit (voltage output of replica pass transistor 316a); receiving, from the select circuit, the first loop control signal at a terminal of the amplifier and the second loop control signal at the terminal of the amplifier (output of 322a is coupled to the second input of 308a); outputting, at an output terminal of the amplifier, an output voltage to the loop control circuit (output of 308a is coupled to the gate of 310a and to the gate of 316a, see [0029] of Hu “the error amplifier 308 controls the gate bias”); and providing the first loop control signal, the second loop control signal, and an LDO regulator output voltage based on the output voltage received at the loop control circuit (pass transistor 310a provides Vout at node 306 and replica pass transistor 316a provides the voltage output of 316a in response to the gate bias received from 308a).
Hu does not disclose providing, to a positive terminal of an amplifier, a standby reference voltage in standby mode and a nap reference voltage in nap mode; selecting, by a select circuit, a first loop control signal from a loop control circuit in the standby mode, and a second loop control signal from the loop control circuit in the nap mode; receiving, from the select circuit, the first loop control signal at a negative terminal of the amplifier in the standby mode and the second loop control signal at the negative terminal of the amplifier in the nap mode; and outputting, at an output terminal of the amplifier, an output voltage to the loop control circuit based on the standby reference voltage and the first loop control signal in the standby mode and the nap reference voltage and the second loop control signal in the nap mode.
However, Setiawan teaches (see Fig. 3) providing, to a positive terminal of an amplifier, a standby reference voltage in standby mode and a nap reference voltage in nap mode (multiplexer 310 provides to the positive input terminal of transconductor 320 a first one of the reference voltage levels vref_1-vref_n in the normal operating mode and a second one of the reference voltage levels vref_1-vref_n in the mode associated with the snooze mode); selecting, by a select circuit, a first loop control signal from a loop control circuit in the standby mode, and a second loop control signal from the loop control circuit in the nap mode (selection circuit 350 selects vfb_main sensed from the regulated voltage vddd in the normal operating mode and vfb_rep from replica loop 330 in the mode associated with the snooze mode); receiving, from the select circuit, the first loop control signal at a negative terminal of the amplifier in the standby mode and the second loop control signal at the negative terminal of the amplifier in the nap mode (output of selection circuit 350 is coupled to the negative input terminal of 320); and outputting, at an output terminal of the amplifier, an output voltage to the loop control circuit based on the standby reference voltage and the first loop control signal in the standby mode and the nap reference voltage and the second loop control signal in the nap mode (transconductor 320 compares vref with vfb and outputs a comparison signal to the gate terminals of the devices of main loop 340 and replica loop 330, see [0036] of Setiawan “transconductor 320 outputs a comparison signal, which is provided to gate terminals”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hu to include providing, to a positive terminal of an amplifier, a standby reference voltage in standby mode and a nap reference voltage in nap mode, selecting, by a select circuit, a first loop control signal from a loop control circuit in the standby mode, and a second loop control signal from the loop control circuit in the nap mode, receiving, from the select circuit, the first loop control signal at a negative terminal of the amplifier in the standby mode and the second loop control signal at the negative terminal of the amplifier in the nap mode, and outputting, at an output terminal of the amplifier, an output voltage to the loop control circuit based on the standby reference voltage and the first loop control signal in the standby mode and the nap reference voltage and the second loop control signal in the nap mode, as taught by Setiawan, because it can help maintain a negative feedback path that regulates the output voltage toward the reference voltage, and because it can help reduce the power consumption of the device in the nap mode.
Regarding claim 18, Hu discloses (see Fig. 3) wherein selecting, by the select circuit, includes receiving an input signal at a select input of the select circuit (transition logic 324a provides the transition signal to the select input of multiplexer 322a, see [0031] of Hu “the output of the transition signal may be used to control the input selection”) for switching between the first loop control signal and the second loop control signal.
Hu does not disclose wherein selecting, by the select circuit, includes receiving a nap input signal at a select input of the select circuit for switching between the first loop control signal in the standby mode and the second loop control signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 5) wherein selecting, by the select circuit, includes receiving a nap input signal at a select input of the select circuit (select input of selection circuit 350 that receives sw_fb receives the snooze signal 510 provided by control circuitry of the integrated circuit, see [0048] of Setiawan “a snooze signal 510 may be used to cause transitions between the different modes”) for switching between the first loop control signal in the standby mode and the second loop control signal in the nap mode (selection circuit 350 provides vfb_main in the normal operating mode and vfb_rep in the mode associated with the snooze mode).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hu wherein selecting, by the select circuit, includes receiving a nap input signal at a select input of the select circuit for switching between the first loop control signal in the standby mode and the second loop control signal in the nap mode, as taught by Setiawan, because it can help switch the device between the standby mode and the nap mode in response to a single signal that indicates the nap mode.
Regarding claim 19, Hu does not disclose providing, by a device control circuit, first control signals to a reference voltage source to provide the standby reference voltage in the standby mode and the nap reference voltage in the nap mode and second control signals to the select circuit to select the first loop control signal in the standby mode and the second loop control signal in the nap mode.
However, Setiawan teaches (see Fig. 3 and Fig. 7) providing, by a device control circuit (regulator control circuit 725 of digital core 720, see [0055] of Setiawan “a regulator control circuit 725 which may provide control signals to control operation”), first control signals to a reference voltage source to provide the standby reference voltage in the standby mode and the nap reference voltage in the nap mode (725 provides the control signal trim_hdreglv[2:0] to multiplexer 310 coupled to the resistor ladder R1-R4, which causes 310 to select one of the reference voltage levels vref_1-vref_n depending upon the mode of operation) and second control signals to the select circuit to select the first loop control signal in the standby mode and the second loop control signal in the nap mode (725 provides the feedback control signal to selection circuit 350, which causes 350 to select vfb_main or vfb_rep).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hu to include providing, by a device control circuit, first control signals to a reference voltage source to provide the standby reference voltage in the standby mode and the nap reference voltage in the nap mode and second control signals to the select circuit to select the first loop control signal in the standby mode and the second loop control signal in the nap mode, as taught by Setiawan, because it can help coordinate the reference voltage and the selected loop control signal from a single determination of the operating mode of the device.
Regarding claim 20, Hu discloses (see Fig. 3) wherein outputting, at an output terminal of the amplifier, the output voltage to the loop control circuit includes receiving the output voltage at a first gate of a first pass transistor (gate of pass transistor 310a receives the output of error amplifier 308a, see [0029] of Hu “the error amplifier 308 controls the gate bias”) that has a first drain/source path (drain/source path of 310a) that includes a first end (drain of 310a) configured to receive an input voltage source (voltage supply 311a) and a second end (source of 310a) electrically coupled to provide the first loop control signal (source of 310a is coupled to node 306 at which Vout is provided to the input of multiplexer 322a), and at a second gate of a second pass transistor (gate of replica pass transistor 316a receives the output of error amplifier 308a) that has a second drain/source path (drain/source path of 316a) that includes a third end (drain of 316a) configured to receive the input voltage source (voltage supply 311a) and a fourth end (source of 316a) electrically coupled to provide the second loop control signal (source of 316a provides the voltage output of 316a to the input of multiplexer 322a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2022/0019253 A1 discloses an adaptable low dropout regulator having a first pass transistor and a second pass transistor with gates commonly coupled to the output of an error amplifier, and a mode selection network that selects the feedback path provided to the inverting input of the error amplifier.
US 2003/0211870 A1 discloses a low dropout regulator having a main voltage reference and a sleep voltage reference that are selected by sleep logic.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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