DETAILED ACTION
The instant action is in response to application filed 25 April 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for priority based on an application filed on 25 April 2024.
Response to Arguments
The 112(b) rejections have been withdrawn.
The drawing objection is withdrawn.
Applicant’s remarks on the merits have been considered but are moot for not considering the reference in the present rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
Claim(s) 1, 5, 6, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Mouret (20200233445) in view of Signh (US 20240319754).
As to claim 1, Mouret discloses (Figure 6) a voltage generator comprising: a temperature-dependent voltage generator (202, 204) configured to generate a voltage that increases with temperature that includes a first transistor stack (M3,M4, Q2) and a second transistor stack (m1, m2, ,5, Q1), each of the first transistor stack and the second transistor stack having a predetermined number of transistors, wherein the number of the transistors of the second transistor stack is greater than the number of the transistors of the first transistor stack; and a reference voltage node (Vref) connected to the temperature-dependent voltage generator (connected via M10 and M11 which mirror M3 and M4) and configured to provide a reference voltage substantially independent of temperature.
Mouret does not explicitly teach wherein the first transistor stack has a gate terminal connected to the reference voltage node.
Singh teaches wherein the first transistor stack (P1) has a gate terminal connected to the reference voltage node (Vref).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device the reference current to a gate of a FET to provide a constant current source.
As to claim 5, Mouret in view of SIgnh does not explicitly disclose wherein the temperature-dependent voltage generator further includes one or more transistor stacks connected parallel to the first transistor stack. However, he does make this obvious. It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (CA7 1977). In this case, the advantage of having more stacks of transistors would be to provide a larger current.
As to claim 6, Mouret in view of Singh does not explicitly disclose wherein the temperature-dependent voltage generator further includes one or more transistor stacks connected parallel to the second transistor stack. However, this is obvious for reasons stated above.
As to claim 7, Mouret in view of Singh teaches wherein the reference voltage of the voltage generator has a temperature coefficient of less than 100 ppm/°C (Fig. 4 shows 1.8mV variation over 100 degrees, which is about 20 microvolts per degree C).
Claim(s) 16-17, 19, 20 are rejected under 35 U.S.C. 103 as being anticipated by Quelen (US 20170153659 ) in view of Singh (US 20240319754).
As to claim 16, Quelen discloses method for generating a temperature-independent reference voltage, the method comprising: generating, by first (N4, N5) and second transistor modules (N6 N7), a first temperature-dependent voltage (V1) that increases with temperature (Fig. 2), wherein the second transistor module has a longer channel length than the second transistor module (See ¶46, the length of N4;N5 is 30 microns and the length of six and seven are 4 microns); generating, by a third transistor module, a second temperature-dependent voltage that decreases with temperature (Node N2/P2); and providing, at a reference voltage node (Vref), a temperature-independent reference voltage based on the first and second temperature-dependent voltages (Vref= V1+ I*VdsN6 + I*VdsN8).
Quelen does not explicitly teach wherein the first transistor stack has a gate terminal connected to the reference voltage node.
Singh teaches wherein the first transistor stack (P1) has a gate terminal connected to the reference voltage node (Vref).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device the reference current to a gate of a FET to provide a constant current source.
As to claim 17, Quelen in view of Singh further comprising: generating a first mirror current (current I generated from P3 in mirror configuration) that flows through the first transistor module; generating a second mirror current (current I generated from P4 in mirror configuration) that flows through the second transistor module proportional to the first mirror current; and generating (¶ 33 “a circuit 101 for generating a bias current I of CTAT”) a temperature-dependent current that flows through the third transistor module.
As to claim 19, Quelen in view of Singh teaches further comprising generating a temperature-dependent current (I) that flows through the third transistor module and that is based on a voltage drop
As to claim 20, Quelen in view of Singh makes obvious generating a mirror current (I) that flows through the resistors. The linear transistor is acting as resistor, and this is obvious for reasons explained above.
Claim(s) 8, 14-15, 21, 22 are rejected under 35 U.S.C. 103 as being unpatentable over by Mouret (US 20200233445) in view of Singh (US 20240319754) and Marinca (US 20180059707)
As to claim 8, Mouret teaches a semiconductor device comprising: a first temperature-dependent voltage generator configured to generate a voltage that increases with temperature (202); a second temperature-dependent voltage generator configured to generate a voltage that decreases with temperature (205); and a reference voltage node (Vref) connected to the first and second temperature-dependent voltage generators (connected via current mirrors, m8/m9 mirror 205 and m10 m11 mirror 202) and configured to provide a reference voltage substantially independent of temperature, wherein the second temperature-dependent voltage generator includes:
Mouret does not explicitly teach a plurality of transistor stacks, but he does make this obvious. . It has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (CA7 1977). In this case, the advantage of having more stacks of transistors would be to provide a larger current.
Mouret does not teach the plurality of transistor stacks of the second temperature dependent voltage generator has a gate terminal connected to the reference voltage and a switch circuit configured to selectively connect one or more of the plurality of transistor stacks to the reference voltage node.
Singh teaches wherein the first transistor stack (P1) has a gate terminal connected to the reference voltage node (Vref).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device the reference current to a gate of a FET to provide a constant current source.
Marinca teaches a switch circuit configured to selectively connect one or more of the plurality of transistor stacks to the reference voltage node (Marinca, Claim 18, “included in a voltage reference circuit comprising: a CTAT component, coupled to the PTAT circuit, and a switching mechanism arranged to selectively connect the PTAT circuit and the CTAT component, such that, in a first mode the PTAT circuit and the CTAT component are connected to provide a temperature independent voltage reference, and in a second mode the PTAT circuit and the CTAT component are not connected to provide a PTAT voltage reference”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device use select switch to provide both PTAT and reference values.
As to claim 13, Mouret in view of Singh and Marinca teaches wherein the second temperature-dependent voltage generator further includes a transistor stack connected parallel to the second transistor stack (this is obvious for reasons similar to claim 5).
As to claim 15, Mouret in view of Singhe and Marinca teaches a supply voltage node (Node M1, M3,, M6, M8, M10) configured to receive a supply voltage, wherein the transistor stack (m6/m7)has a first source/drain terminal and a gate terminal connected to each other (m7) and to the reference voltage node (current mirrored via M8/M9) and a second source/drain terminal connected to the supply voltage node.
As to claim 21, Mouret in view of Singhe and Marinca teaches wherein the plurality of transistor stacks of the second temperature-dependent voltage generator further includes a first source/drain terminal connected to the gate terminal and the reference node (Vref is attached to the CTAT and PTAT)
As to claim 22, Mouret in view of Singhe and Marinca teaches wherein the plurality of transistor stacks of the second temperature-dependent voltage generator further includes a second source/drain terminal connected to the gate terminal and the reference node (Vref is attached to the CTAT and PTAT)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Quelen (US 20170153659) in view of Singh (US 20240319754) and Kundu (US 11474552).
As to claim 18, Quelen in view of Singh teaches generating a current and a third mirror current. He does not explicitly disclose generating a substantially constant current; generating a third mirror current proportional to the substantially constant current; and biasing the first and second transistor modules using the third mirror current.
Kundu teaches generating a substantially constant current (212); generating a mirror current proportional to the substantially constant current (208); and biasing transistor modules (M1, M2) using the mirror current.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to mirror biased current sources as disclosed in Kundu to reduce dependence on the supply voltage.
Allowable Subject Matter
Claims 2-4, 9-11 would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the prior art fails to disclose: “further comprising: a first current mirror circuit configured to generate a first current and a second current proportional to the first current; a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein: the first transistor stack has a first source/drain terminal connected to the first current mirror circuit, a second source/drain terminal connected to the second current mirror circuit, and the second transistor stack has a first source/drain terminal connected to the first current mirror circuit, a second source/drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 9, the prior art fails to disclose: “further comprising: a first current mirror circuit configured to generate a first current and a second current proportional to the first current; a second current mirror circuit configured to generate a third current and a fourth current proportional to the third current, wherein: the first temperature dependent voltage generators include a first transistor stack and a second transistor stack, the first transistor stack has a first source/drain terminal connected to the first current mirror circuit, a second source/drain terminal connected to the second current mirror circuit, and a gate terminal connected to the reference voltage node; and the second transistor stack has a first source/drain terminal connected to the first current mirror circuit, a second source/drain terminal connected to the second current mirror circuit, and a gate terminal connected to the first current mirror.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, new claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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